T8531A/T8532 Agere Systems, Inc., T8531A/T8532 Datasheet - Page 10

• Manufacturer Part Number: T8531A/T8532
• Description: Multichannel Programmable Codec Chip Set
• Manufacturer: Agere Systems, Inc.

Codec Chip Set
Pin Information
Table 2. T8531A Pin Descriptions
Note: TI = TTL input, TO = TTL output; CI = CMOS input, CO = CMOS output; AI = analog input, AO = analog output; I
10
Number
43, 45,
42, 44,
36, 38
35, 37
device is included on this lead.
29
30
27
28
39
40
11
13
24
20
17
22
OSDX[3:0]
OSDR[3:0]
SCKSEL
UPDO
OSCK
STSXB
Name
UPCK
OSFS
UPCS
UPDI
V
SDR
V
SCK
DDA
SSA
(continued)
Type
CO
CO
CO
TO
TO
TI
CI
—
—
TI
TI
TI
TI
TI
u
Control Data Interface Input. The microcontroller sends control register
address and data to the T8531A through this pin.
Control Data Interface Output. The microcontroller receives control regis-
ter contents from this pin. Inactive state is high impedance.
Control Data Interface Clock. Bit clock for the control interface. Speed is
limited to 4.096 MHz.
Control Interface Chip Select (Active-Low). This active-low input enables
the control interface.
Oversampled Transmit Data. Four channels of 1 Msamples/s - transmit
data are received from the T8532 chips through each of these pins. The data
rate is 4.096 MHz.
Oversampled Receive Data. Four channels of 1 Msamples/s - receive
data is transmitted to the T8532 chips on each of these pins. The data rate is
4.096 MHz.
4.096 MHz Clock. Clock for data transfer to/from T8532 chips.
Oversampling Sync. 8 kHz synchronization pulse for data transfer
to/from T8532 chips.
Synthesizer V
Synthesizer Ground. Ground connection for the clock synthesizer block.
Backplane Drive Enable (Active-Low). Active when SDX is transmitting
valid data; high impedance otherwise. This pin provides an enable signal for
a backplane line driver.
Master Clock Input. This is the bit clock used to shift data into and out of the
SDR and SDX pins. It is the input to the clock synthesizer and is used to
generate all internal clocks. Rate is 4.096 MHz.
Master Clock Select Input. A logic low selects the 2.048 MHz SCK. A logic
high selects the 4.096 MHz SCK. An internal pull-up device is included, pro-
viding 4.096 MHz SCK operation with no external connections.
Receive PCM Input. The data on this pin is shifted into the T8531A on the
falling edges of SCK. Data is only entered for valid time slots as defined in
the TSA registers.
DD
. Power supply for clock synthesizer block.
Name/Function
Agere Systems Inc.
u
indicates a pull-up
May 2001