T8531A/T8532 Agere Systems, Inc., T8531A/T8532 Datasheet - Page 18

• Manufacturer Part Number: T8531A/T8532
• Description: Multichannel Programmable Codec Chip Set
• Manufacturer: Agere Systems, Inc.

Codec Chip Set
Chip Set Functional Description
(continued)
DSP Engine Timing
The Time-Slot Control Word
The DSP engine works in time-slot order. The TSA
function is performed by the decimator/interpolator.
The DSP engine is not required to reorder the data in
any way. The advantages of this approach are that the
group delay introduced by the TSA function is very
small, and the DSP code needed for context switching
is small. When the microprocessor assigns a time slot
via the TSA RAM, it also has to issue a new time-slot
control word (TCW) instruction to the DSP engine to
enable the time slot to link to the correct ac coefficients.
The TCW contains the information shown in Tables 5A
and 5B. The TCW is only looked at when a time slot is
inactive. The initial setup of the TCWs assumes chan-
nel-order time-slot assignment.
Table 5A. Bit Map for DSP Engine Time-Slot Control Word
Table 5B. Bit Map for Default Per-Board Coefficient Tables
Table 6. DSP Engine RAM Map for Time-Slot Information Table 0
18
18
data storage
Bit 7
Variable
rx_rtn_0
tx_rtn_0
0
0
1
1
tcw_0
Register Bit
0—3
6—7
4
5
Bit 6
0
1
0
1
(continued)
Use Default Per-Board Coefficient Tables
Address of Transmit ac Routine
Address of Receive ac Routine
Default Table 1 Coefficient Set
Default Table 2 Coefficient Set
Default Table 2 Coefficient Set
Do Not Select Default Tables
Time-slot Control Word
Modify Coefficients
Channel Number
Go to Powerup
Function
Reserved
Mode
Function
Operations Performed by the DSP Engine at
T8531A Start-Up
The DSP engine performs its start-up code after it has
been reset. All interrupts are disabled. First, the DSP
engine computes the checksum for its ROM and RAM
to verify their integrity. Next, the DSP engine walks
through each time-slot information table and sets the
data buffer and coefficient pointers. The DSP engine
RAM is set up for channel-order time-slot assignment,
i.e., table 0 points to channel_0 and so on. The start-up
settings for the Time-Slot Information Table (i.e., for
time slot 0) are shown in Table 6.
The first 16 locations of RAM bank 1 hold the channel
address table, where pointers to the start of the coeffi-
cient space for each channel are held. These pointers
are set up during the start-up routine. Pointers to the
three sets of default coefficients are also set up. The
DSP engine then walks through all 16 ac coefficient
tables and sets them to their initial values as shown in
the previous section. The RX and TX filter coefficients
(one set for all 16 lines) are taken from ROM and writ-
ten to their RAM locations.
The DSP engine takes about 3 ms to execute the start-
up code. At the end of the code, the interrupt system is
enabled and the DSP engine enters sleep mode.
channel_(time-slot number)
Initial Value
Initialized Address
rpath_inactive
tpath_inactive
See above
0
0
0
Agere Systems Inc.
NA
May 2001