T8531A/T8532 Agere Systems, Inc., T8531A/T8532 Datasheet - Page 13

• Manufacturer Part Number: T8531A/T8532
• Description: Multichannel Programmable Codec Chip Set
• Manufacturer: Agere Systems, Inc.

May 2001
Chip Set Functional Description
(continued)
Receive Path
In the receive direction, the signal received from the
system interface is converted to a 16-bit linear PCM sig-
nal.
Receive Path Filtering
The 16-bit linear PCM signal is filtered and interpolated
to 16 ksamples/s to meet the receive signal loss charac-
teristics. This filter smooths the data following interpola-
tion from 8 ksamples/s to 16 ksamples/s. The filter can
also serve as an equalizer for frequency response alter-
ation. This is required for complex termination imped-
ance cases when using a current feed, voltage-sensed
SLIC.
One of two receive filters can be used, the receive filter
and the extended receive filter. The receive filter has
two poles and three zeros. This filter can be used to
minimize downloadable code (to use this receive filter,
select the T7531x codec in the Aquarium coefficient
software). The extended receive filter provides more
flexibility in coefficient optimization by providing three
poles and three zeros. The Aquarium coefficient soft-
ware defaults to the extended receive filter when the
T8531x codec is selected.
Digital Receive Gain
The receive absolute and relative gains are specified as
15-bit binary numbers representing their linear magni-
tude. These gains default to 4000 hex. This equates to a
0 dB gain for the relative gain but equates to a
–0.211 dB gain for the absolute gain. For a 0 dB gain,
program the absolute gain for 4193 hex. Gain can be
varied from minus infinity dB (0) (0000 hex) to 6 dB for
relative gain or to 5.8 dB for absolute gain (7FFF hex).
The relative gain control allows for TLP adjustment with-
out hybrid balance or termination coefficient modifica-
tion.
Interpolator and Digital Sigma-Delta Modulator
The sampling frequency of the receive signal from the
digital gain adjustment is increased from 16 kHz to
64 kHz by the interpolator, which removes most of the
high-frequency signal images above 8 kHz. The interpo-
lator also maps each of 16 time slots to the appropriate
line channel through the digital sigma-delta modulator.
The digital sigma-delta modulator converts the interpo-
lated signal to a 1.024 MHz bit stream which is then sent
to the T8532 device.
Agere Systems Inc.
Decoder, Filters, and Receive Amplifier
Receive data enters the T8532 on pins OSDR[1:0] at
4.096 MHz; four channels are time-division multiplexed
onto each pin. The data is demultiplexed into eight indi-
vidual channels. The processed signal for each chan-
nel passes through switched-capacitor D/A and
reconstruct filters, followed by a smoothing filter. A pro-
grammable gain amplifier is included, followed by an
output amplifier capable of driving a 50 k load to
ferential at peak overload. For single-ended operation,
the load must be ac coupled to VRP (or VRN).
Other Chip Set Functions
Voltage Reference
The T8532 has a precision on-chip voltage reference
which ensures accurate and highly stable transmission
levels.
Hybrid Balance
The hybrid balance function is provided as a digital
block in the T8531A
The T8531A implements a 9-tap FIR and a single-pole
IIR digital balance filter in which a replica of the echo is
digitally subtracted from the transmit plus near-end
echo signal. The coefficients are user programmable
on a per-line basis via the microprocessor interface.
Analog Termination Impedance Synthesis
Termination impedance matching is implemented to
maximize the power transfer capability at the loop inter-
face and to minimize signal reflections between the
transmit and receive paths.
The resistive component, implemented in the T8532
device, comprises a variable attenuated path between
VTX and VRP. The capacitive component is imple-
mented in the digital domain.
Analog termination impedance (ATI) is provided with 16
gain settings to match a voltage drive/current sense
line interface circuit with the following characteristics:
Z
where Z
the resistance of each protection resistor (for stability
R
SLIC receive gain, and A
The polarity of the A
swing on VTX gives a positive voltage swing on VRP).
The gain values are shown in Table 26; gain tolerances
are 2%. Differential receive output is assumed.
1.58 V single-ended (relative to VOS) or 3.16 V dif-
T
P
= 2R
50 ), G
P
T
+ G
is the termination impedance in ohms, R
TX
TX
* G
is the SLIC transmit gain, G
RX
T
gain is positive (positive voltage
* A
T
T
is the T8532 feedback gain.
Codec Chip Set
RX
is the
P
is
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