T8531A/T8532 Agere Systems, Inc., T8531A/T8532 Datasheet - Page 14

• Manufacturer Part Number: T8531A/T8532
• Description: Multichannel Programmable Codec Chip Set
• Manufacturer: Agere Systems, Inc.

Codec Chip Set
Chip Set Functional Description
(continued)
Other Chip Set Functions
Digital Termination Impedance Synthesis
The CTZ filter in the T8531A synthesizes complex ter-
mination impedances. The CTZ filter utilizes alpha and
beta coefficients (board control words 4 and 5, respec-
tively) to perform the synthesis. One set of alpha beta
coefficients is required for each termination impedance
and balance network.
Alpha bits [9:0] represent the RC time constant of the
impedance that the filter is going to synthesize. The
bits are formatted as two’s complement. Alpha bits
must be a nonzero value. Beta bits [7:0] represent the
dc gain of the filter. Beta coefficients are also formatted
as two’s complement. Setting beta equal to zero turns
off the CTZ function.
There is a constraint on the value of the protection
resistor with regard to termination impedance synthesis
and hybrid balance. For synthesis to operate properly,
the combined series resistance of the tip protection
resistor and the ring protection resistor must be 100
or greater.
Loopback Modes
There are four loopback modes in the T8532.
The first two loopback modes are controlled by the all-
channel test (ACT) register. ACT bits 0 and 1 place all
eight channels into loopback mode. Analog and digital
loopback are described and shown in block diagram
form in Table 29. Analog loopback allows one to check
functionality from Tip/Ring up to and including the
T8532. Digital loopback allows the T8531A to check
T8532 functionality.
The third loopback mode is used in the autocalibration
sequence (control register 2). This mode provides a
loopback between a selected channel and channel four
of a given T8532. The channel to be calibrated is
selected via control register 1 (see Table 27). Channel
four is the only channel in the T8532 that is trimmed for
gain accuracy. Every other channel uses channel four
as a reference and is calibrated to it during the autocal-
ibration sequence.
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(continued)
The fourth loopback mode is a digital loopback mode
located in control register 1. This operates like the digi-
tal loopback mode described in the notes for the ACT
register (table 29). Unlike the ACT register, this digital
loopback mode is selectable per channel. This loop-
back mode can be used to check T8532 functionality
from the T8531A device. It is also used during the cali-
bration sequence.
There is one loopback mode in the T8531A Loopback
at the oversampled data interface is controlled by
board control word 1. This mode allows the T8531A to
test itself. When bit 0 of 0x1FFE is selected, all 16
channels of octal interface receive data (OSDRn) are
looped back to the T8531A transmit inputs (OSDXn).
Interchip Control Interface
The control interface is a 4-pin interface used to send
control information to the T8532 from the T8531, and to
read back the control register contents. The pins con-
sist of a chip select input (CCS0/CCS1), a data input
(CDI), and a data output (CDO). The transfer of control
data is synchronous with the 4.096 MHz OSCK, which
is also used for oversampled data transfer.
T8531A Functional Blocks
Clock Synthesizer
The clock synthesizer block is a phase-lock loop (PLL)
circuit which takes SCK supplied by the backplane and
uses it to produce the 81.92 MHz DSP engine clock.
The input clock, SCK, can be 2.048 MHz or 4.096 MHz.
An on-chip clock synthesizer has the advantages
shown below:
A clock generator block takes the PLL output and
divides it down to produce all the lower-frequency
clocks used by the T8531A and T8532.
Precludes the need for extra clocks to be fed over
the backplane.
Constrains the high-speed DSP engine clock within
the device.
Synchronizes all clocks used on the line card to the
backplane clock, thus reducing board noise due to
beat frequencies.
Agere Systems Inc.
May 2001