T8531A/T8532 Agere Systems, Inc., T8531A/T8532 Datasheet - Page 11

• Manufacturer Part Number: T8531A/T8532
• Description: Multichannel Programmable Codec Chip Set
• Manufacturer: Agere Systems, Inc.

May 2001
Agere Systems Inc.
Pin Information
Table 2. T8531A Pin Descriptions (continued)
* The DSP is not configured for boundary scan operation.
Note: TI = TTL input, TO = TTL output; CI = CMOS input, CO = CMOS output; AI = analog input, AO = analog output; I
2, 9, 15, 18, 26,
25, 31, 34, 46,
32, 33, 41, 47,
3, 10, 16, 19,
1, 12, 14, 64
50, 56, 62
49, 57, 63
Number
up device is included on this lead, I
53, 52
23
21
54
51
48
59
60
61
55
58
7
4
5
6
8
TSTCLK
CCS[1:0]
JTESTB
T_SYNC
HIGHZB
Name
CK16
(continued)
RSTB
CDO
TEST
TDO
TMS
SDX
TCK
SFS
CDI
TDI
V
V
NC
DD
SS
Type
d
CO
CO
CI
CO
CI
TO
TI
TI
TO
TI
TI
TI
TI
CI
—
—
—
TI
TI
indicates that a pull-down device is included on this lead.
u
u
u
u
u
u
u
u
Transmit PCM Output. This pin remains in the high-impedance state
except during the transmit time slots as defined in the TSA registers.
Data is shifted out on the rising edge of SCK.
Frame Sync. Active-high pulse or square wave with an 8 kHz pulse
repetition rate. The rising edge defines the start of the transmit and
receive frames.
T8532 Control Data Output. Control register information for the T8532
chips. Data is valid only when either CCS0 or CCS1 is low.
T8532 Control Data Input. Control register information from the T8532
chips. Data is valid only when either CCS0 or CCS1 is low. An internal
pull-up device is provided.
Control Interface Chip Select (Active-Low). These active-low outputs
select one of the associated T8532 chips.
JTAG Test Port*-Common Test Clock. Rate 20 MHz.
JTAG Test Port*-Serial Data Input. A pull-up device is provided.
JTAG Test Port*-Serial Data Output.
JTAG Test Port*-Mode Select. A pull-up device is provided.
JTAG Test. Used for factory testing. Do not make any connection to this
pin. A pull-up device is provided.
3-State Control Pin (Active-Low). When pulled low, the device output
pins go into a high-impedance state. A pull-up device is provided.
Test Mode Input (Active-Low). This input allows bypass of clock synthe-
sizer and uses TSTCLK to drive the chip. A pull-up device is provided.
16 MHz Clock Output. 16.384 MHz clock output (50% duty cycle). This
clock is present at all times and can be used to drive a host processor.
Test Clock.
No Connect. This pin may be used as a tie point.
Test Sync (Active-Low). Used for factory testing. Do not make any con-
nection to this pin. A pull-up device is provided.
Reset (Active-Low). A logic low initiates reset. A pull-up device is pro-
vided.
5 V Digital Power Supply. Power supply decoupling capacitors (0.1 F)
should be connected from each V
located as close as possible to the device pins.
Digital Ground.
Name/Function
DD
pin to ground. Capacitors should be
Codec Chip Set
u
indicates that a pull-
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