T8531A/T8532 Agere Systems, Inc., T8531A/T8532 Datasheet - Page 40

T8531A/T8532

Manufacturer Part Number

T8531A/T8532

Description

Multichannel Programmable Codec Chip Set

Manufacturer

Agere Systems, Inc.

Datasheet

1.T8531AT8532.pdf (50 pages)

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Codec Chip Set

Software Interface

Table 33. Bits 15:8 of T8531A Board Control Word 1 at 0x1FFE

Table 34. Bits 7:0 of T8531A Board Control Word 1 at 0x1FFE

Notes:

All bits in board control register 1 will be zeros upon hardware reset.

In OSD loopback mode, OSDR0, OSDR1, OSDR2, and OSDR3 are looped back with a delay of two OSCLK clock cycles to OSDX0, OSDX1,

OSDX2, and OSDX3, respectively.

Test modes are for production testing only.

the sign bit, bits 2 through 4 are the chord bits, and bits 5 through 8 are the interval bits. In linear mode, the -law/A-law conversion in the PCM

interface block is disabled and 16 bits of linear PCM data are provided. In linear mode, bit 1 is the MSB and the sign bit, bits 2 through 14 are

the intervals, and bits 15 and 16 are insignificant. Each interval represents 0.0001362745 Vrms with 8031 intervals being the maximum signal

output of 3 dBm0. Negative values are two’s complement of positive values.

X = don’t care.

-law/A-law companding mode provides 8 bits of PCM data with the first bit (bit 1) defined as the MSB and the last bit (bit 8) as the LSB. Bit 1 is

—

Bit Number

—

(continued)

—

A-law, including even bit inversion

C1C0 = card address in binary

A-law, no even bit inversion

Nondelayed data timing

Delayed data timing

Nodecim test mode

RX dither circuit off

Normal operation

Loopback at OSD

TZ test mode

Linear mode

Soft reset

Function

Reserved

Function

-law

Agere Systems Inc.

May 2001

T8531A/T8532 Agere Systems, Inc., T8531A/T8532 Datasheet - Page 40

T8531A/T8532

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