T8531A/T8532 Agere Systems, Inc., T8531A/T8532 Datasheet - Page 20

• Manufacturer Part Number: T8531A/T8532
• Description: Multichannel Programmable Codec Chip Set
• Manufacturer: Agere Systems, Inc.

Codec Chip Set
Chip Set Functional Description
(continued)
DSP Engine Timing
Changing DSP RAM Space of an Active Time Slot
The microprocessor is only allowed to change four
RAM locations for an active time slot:
Absolute gains and time-slot assignment can only be
altered when the time slot is inactive. Note that the
DSP engine does not check the TCW of active time
slots.
Following the initial powerup, the line card is likely to be
in service without being reset for as long as it continues
to operate trouble-free. Therefore, the microprocessor
has the option of continuously monitoring the variables
it has programmed by reading them back from the DSP
engine/microprocessor interface and rewriting them.
DSP Engine Memory Requirements
The size of the DSP engine internal dual-port RAM is
4K x 16-bit words per DSP engine. RAM storage is
used for user-programmable variables and for interme-
diate storage of the data being processed by the
device. The RAM memory map is given in Table 18.
The on-chip ROM is used for both program and data.
The DSP engine firmware is ROM based. The hard-
ware development system code is also ROM based.
The DSP engine ROM memory map is given in
Table 41.
Table 7. Summary of Microprocessor Commands for Control of T8531A Data Processing
20
20
Bulk TSA register download & BCW2
Individual TSA register download
Coefficient download
Set TCW to use/share coefficients
Enable time slot via TCW (fixed TSA)
Enable time slot via TCW (dynamic TSA)
Disable time slot
Change gain value
Relative transmit gain
Relative receive gain
Address of receive ac routine
Address of transmit ac routine
already downloaded to default tables
Function Required
(continued)
Number of Commands
16 per channel
1 per gain
17
1
1
1
2
1
T8531A Reset and Start-Up
The chips support both hardware and software reset.
Hardware Reset
The T8531A reset functions are handled by the reset
control block. Hardware reset occurs if the board is
powered up with RSTB low. Since RSTB has a Schmitt
trigger buffer with an internal pull-up, a capacitor
attached external to the RSTB pin causes the pin to
pull high after a specified period of time. For power-on
reset, the T8531A requires that this period of time be
>1 ms to give the on-chip clock synthesizer block time
to start producing clock edges for the T8531A and
T8532 chips (although it may not have reached its final
accuracy yet). Successful hardware reset of the device
requires that:
1. The PCM bus signals SCK and SFS should be valid
2. V
If, during normal operation, V
minimum value, V
described above must be repeated.
Hardware reset occurs if RSTB is pulsed high-low-high
for 1 ms during normal operation (i.e., no loss of
power).
at the start of the 1 ms power-on reset period.
at least 200 ms prior to commencing power-on reset
to ensure that the JTAG controller powerup reset cir-
cuit has had time to clear the JTAG controller.
DD
(and therefore RSTB) should have been low for
Prior to activating a time slot via the TCW
Start-up or when time slot is inactive
Start-up or when time slot is inactive
DD
When time slot is inactive
When time slot is inactive
min, the power-on reset procedure
When time slot is active
When Issued
Any time
Start-up
DD
falls below the defined
Agere Systems Inc.
May 2001