T8531A/T8532 Agere Systems, Inc., T8531A/T8532 Datasheet - Page 3

• Manufacturer Part Number: T8531A/T8532
• Description: Multichannel Programmable Codec Chip Set
• Manufacturer: Agere Systems, Inc.

May 2001
Figures
Figure 1. System Block Diagram .................................1
Figure 2. Block Diagram of T8532 Octal Converter.....4
Figure 3. Block Diagram of One T8532 Analog
Figure 4. T8531A Block Diagram ................................5
Figure 5. T8531A Digital ac Path.................................6
Figure 6. Control, PCM, and Octal Interfaces..............6
Figure 7. T8532 64-Pin MQFP ....................................7
Figure 8. T8531A 64-Pin TQFP...................................9
Figure 9. Timing Characteristics of PCM Interface
Figure 10. Timing Diagram for Microprocessor
Figure 11. Line Card Solution Using the L7585
Figure 12. Line Card Solution Using the L9215G
Figure 13. Line Card Solution Using the L9310G
Figure 14. Common 2.4 V Voltage Reference...........47
Tables
Table 1. T8532 Pin Descriptions ................................. 8
Table 2. T8531A Pin Descriptions ............................. 10
Table 3. Active Time-Slot Spacing in a PCM
Table 4. DSP Engine RAM Map for Channel_0 ac
Table 5A. Bit Map for DSP Engine Time-Slot
Table 5B. Bit Map for Default Per-Board
Table 6. DSP Engine RAM Map for Time-Slot
Table 7. Summary of Microprocessor Commands
Table 8. Digital Interface............................................ 25
Table 9. Analog Interface .......................................... 25
Table 10. T8532 Power Dissipation...........................26
Table 11. T8531A Power Dissipation ........................ 26
Table 12. Gain and Dynamic Range ......................... 26
Table 13. Noise (per Channel) ..................................28
Table 14. Distortion and Group Delay ....................... 29
Table 15. Crosstalk.................................................... 29
Table 16. PCM Interface Timing ............................... 30
Table 17. Serial Control Port Timing ........................ 32
Agere Systems Inc.
Bus Frame ................................................... 15
Path Coefficients ......................................... 17
Information Table 0...................................... 18
for Control of T8531A Data Processing....... 20
Channel........................................................4
Assuming 2.048 MHz SCK Rate ................31
Control Word............................................. 18
Coefficient Tables...................................... 18
Write/Read to/from the DSP on the
Control Interface.......................................32
SLIC .........................................................44
SLIC .........................................................45
SLIC .........................................................46
Table of Contents
Page
Page
Table 18. DSP Engine RAM Memory Map ................33
Table 19. T8531A Time-Slot Assignment Memory
Table 20A. Bit Map for T8531A Time-Slot Assignment
Table 20B. Bit Map for CTZ Disable and Null
Table 21. T8531A Channel Register Memory Map
Table 22. T8531A Channel Register Memory Map
Table 23. Bit Map for T8532 Powerup/Powerdown
Table 24. Bit Map for T8532 Channel Control
Table 25. T8532 Control Register 1: Transmit
Table 26. T8532 Control Register 1: Analog
Table 27. T8532 Control Register 1: Digital
Table 28. Bit Map for T8532 All Channel Test
Table 29. Bits 3:0 of T8532 All Channel Test
Table 30. Bit Map for T8532 Channel Control
Table 31. T8532 Control Register 2: Receive Gain ...39
Table 32. T8531A Control Register Map ...................39
Table 33. Bits 15:8 of T8531A Board Control Word 1
Table 34. Bits 7:0 of T8531A Board Control Word 1
Table 35. Bits 15:9 of T8531A Board Control Word 2
Table 36. Bits 8:0 of T8531A Board Control Word 2
Table 37. Bits 15:0 of T8531A Board Control Word 3
Table 38. Bits 15:0 of T8531A Board Control Word 4
Table 39. Bits 15:0 of T8531A Board Control Word 5
Table 40. Bits 15:0 of T8531A Reset of
Table 41. DSP Engine ROM Memory Map................42
Table 42. Transmit Path Group Delay vs. Bit Offset ..50
(continued)
Map ...........................................................35
for T8532 Device 0 ...................................36
for T8532 Device 1 ...................................36
Registers at 0x1500—0x1507 and
0x1540—0x1547 .......................................37
Register 1 at 0x1508—0x150F and
0x1548—0x154F .......................................37
Gain ...........................................................37
Termination Impedance.............................37
Loopback ...................................................38
Register at 0x1510 and 0x1550.................38
Register at 0x1510 and 0x1550.................38
Register 2 at 0x1518—0x151F and
0x1558—0x155F .......................................39
at 0x1FFE ..................................................40
at 0x1FFE ..................................................40
at 0x1FFC..................................................41
at 0x1FFC..................................................41
at 0x1FFA ..................................................41
at 0x1FF8 ..................................................41
at 0x1FF6 ..................................................41
Microprocessor Commands at 0x7FFF .....41
Registers at 0x1400—0x140F.................35
Channel...................................................35
Codec Chip Set
3