T8531A/T8532 Agere Systems, Inc., T8531A/T8532 Datasheet - Page 8

• Manufacturer Part Number: T8531A/T8532
• Description: Multichannel Programmable Codec Chip Set
• Manufacturer: Agere Systems, Inc.

Codec Chip Set
Pin Information
Table 1. T8532 Pin Descriptions
Note: TI = TTL input, TO = TTL output; CI = CMOS input, CO = CMOS output; AI = analog input, AO = analog output; I
8
2, 6, 12, 16, 33,
3, 5, 13, 15, 34,
1, 7, 11, 17, 32,
31, 39, 41, 49
64, 8, 10, 18,
9, 19, 27, 30,
20, 22—26,
38, 42, 48
37, 43, 47
36, 44, 46
40, 50, 63
4, 14, 21,
Number
35, 45
device is included on this lead, I
60, 59
61, 58
28, 29
51
62
57
56
54
52
53
55
OSDR[1:0]
OSDX[1:0]
VRTX[7:0]
VRP[7:0]
VRN[7:0]
VTX[7:0]
OSCK
Name
OSFS
RSTB
CDO
V
V
V
V
CCS
CDI
(continued)
NC
DDA
DDD
SSA
SSD
d
Type
CO
CO
indicates a pull-down device is included on this lead.
AO
AO
TI
AI
AI
—
—
—
—
CI
CI
CI
CI
CI
—
u
Analog Input. Transmit signal voltage to be encoded.
Transmit Reference Voltage. 2.4 V reference. Each pin must have a sep-
arate supply associated with the corresponding VTX pin.
Noninverting Receive Output. This pin can drive high-impedance loads
either differentially or single ended. It is the complement of the VRN output.
Inverting Receive Output. This pin can drive high-impedance loads either
differentially or single ended. It is the complement of the VRP output.
5 V Analog Power Supply. Power supply decoupling capacitor (0.1 F)
should be connected from each V
should be located as close as possible to the device pins.
Analog Ground.
5 V Digital Power Supply. Decouple with a 0.1 F capacitor to digital
ground.
Digital Ground.
Oversampled Transmit Data. Four channels of 1.024 MHz - transmit
data is transmitted to the T8531A through each of these pins. The data rate
is 4.096 MHz.
Oversampled Receive Data. Four channels of 1.024 MHz - receive
data is received from the T8531A on each of these pins. The data rate is
4.096 MHz.
Interface Clock. The 4.096 MHz clock that enters this pin from the T8531A
serves as the bit clock for all the oversampled data transmission between
this chip and the T8531A This is the master clock input for the T8532.
Interface Frame Sync. This signal serves as the frame sync for the over-
sampled data interface between the T8532 and the T8531A
Control Data Interface Input. The T8531A sends control register address
and data to the T8532 through this pin. One address byte and one data
byte are accepted each time CCS is toggled.
Control Data Interface Output. Control register contents are clocked out
through this pin.
Control Interface Chip Select (Active-Low). This active-low input
enables the control interface.
Reset (Active-Low). This input must be pulled high for normal operation.
When pulled momentarily low (at least 1 s) while OSCK is active, all pro-
grammable registers in the device are reset to the states specified under
powerup initialization. This pin has an internal pull-up resistor.
No Connect. No connection to chip. These pins can be used as logic level
tie points.
Name/Function
DDA
pin to analog ground. Capacitors
Agere Systems Inc.
u
indicates a pull-up
May 2001