T8531A/T8532 Agere Systems, Inc., T8531A/T8532 Datasheet - Page 16

• Manufacturer Part Number: T8531A/T8532
• Description: Multichannel Programmable Codec Chip Set
• Manufacturer: Agere Systems, Inc.

Codec Chip Set
Chip Set Functional Description
(continued)
T8531A Functional Blocks
A pause therefore exists between the external control-
ler issuing an address and receiving a data read back.
The data rate of 2.048 MHz allows 256 SCK cycles in a
frame, i.e., eight address/data pairs with no pause
between words. Since the DSP engine can process
only one interrupt every 7.8 s, the T8531A requires a
separation between address and data on read and
write instructions to the microprocessor interrupt (see
Figure 10). This, in effect, requires UPCK to be
gapped. Addresses 0x1400 refer to registers or TSA
RAM external to the DSP engine. If the address word
from the microprocessor is 0x1400 through 0x140F, it
activates the TSA state machine. If the address word
from the microprocessor is 0x1500 through 0x15FF, it
activates the T8532 control state machine.
Microprocessor data and address words can be
flushed out of the T8531A by addressing 0x7FFF with
data word 0xFFFF (see Table 40).
T8532 Octal Control Interface
The two T8532 chips cannot be accessed by the micro-
controller directly; the T8532’s registers are all
accessed via the T8531A microprocessor interface.
The microprocessor communicates serially with the
T8532 by simply writing or reading 16-bit address and
16-bit data. The octal control interface block translates
this address and data into 8-bit address and 8-bit data
needed by the T8532. The octal control interface block
waits until the microprocessor interface block receives
all 16 bits of the address word and determines whether
this is a read or write operation by looking at bit 15. If
this is a write operation for a T8532 chip, it receives
another 16-bit data word.
T8531A Time-Slot Assignment (TSA)
The TSA block contains a 16 x 6 dual-port RAM which
is readable or writable via the microprocessor inter-
face. Table 18 gives the bit map for TSA RAM words.
The TSA RAM is in time-slot order, i.e., location
0x1400 is for time slot 0 and 0x1401 for time slot 1 and
so on. The low 4 bits (B3—B0) indicate which of the 16
possible channel numbers is assigned to this time slot.
The time-slot assignment is controlled by the micropro-
cessor writing to address 0x1400 through 0x140F.
16
16
(continued)
The TSA block also generates the control signals and
flags used to synchronize the TSA, interpolator and
decimator, and T8532 interface blocks. The TSA RAM
is not preinitialized, so the microprocessor is required
to write to all 16 locations of the TSA RAM at start-up to
ensure proper operation. Twice a frame, the TSA state
machine reads the entire TSA RAM from top to bottom
in sequence and sends the contents of each RAM loca-
tion to the interpolator as channel numbers for RX
channels. The TSA state machine performs the same
procedure for the decimator to provide it with the TX
channel numbers. By performing TSA at the oversam-
pled sigma-delta rate, round trip group delay is signifi-
cantly minimized.
DSP Engine Timing
The DSP engine processes all 16 lines every frame. In
order to simplify synchronization of data exchanges,
the processing frame is broken into 16 equal time seg-
ments of 7.8 s each. The ROM code is identical for
each time segment.
Synchronization between the engine and the rest of the
chip is enforced by the system interface block, which
issues an interrupt every 7.8 s. This interrupt is the
only unmasked interrupt processed by the engine. The
interrupt service routine forces the ROM code to
branch to the start of the processing loop.
T8531A Program Structure
The DSP engine firmware performs three types of
operations:
1. Signal processing of the ac path data.
2. RAM accesses initiated by the microprocessor
3. Data and program flow operations.
The signal processing algorithms performed by the
T8531A are implemented in firmware and are held in
ROM.
Many firmware parameters are user programmable via
the microprocessor interface. Interrupts from the micro-
processor interface are handled once every time seg-
ment (7.8 s), and the appropriate accesses are made
to the DSP engine RAM registers.
interface.
Agere Systems Inc.
May 2001