T8531A/T8532 Agere Systems, Inc., T8531A/T8532 Datasheet - Page 17

• Manufacturer Part Number: T8531A/T8532
• Description: Multichannel Programmable Codec Chip Set
• Manufacturer: Agere Systems, Inc.

May 2001
Chip Set Functional Description
(continued)
DSP Engine Timing
Control of the DSP Engine via the Microprocessor
Interface
There are four types of commands that the external
controlling device may issue to the DSP engine:
1. Downloading data to RAM.
2. Activating and deactivating lines.
3. Changing the RX and TX routine to be run.
4. Periodic read and/or refresh of RAM space.
All of these commands must only involve reading and
writing to the DSP RAM so that the DSP engine does
not have to perform test- and branch-type operations
when a microprocessor interface command is received.
The complete memory map for the DSP engine RAM is
given in Table 18. The microprocessor interface is
allowed to read any RAM location in the DSP engine
and to write to specified addresses.
The DSP Engine Time-Slot Information Tables
In the T8531, the DSP engine RAM has been set up to
contain 16 tables which hold the pointers to the ac
coefficients and data buffers required to process each
time slot. Each table starts on a 32-word boundary and
is accessed in the firmware using direct addressing
instructions. Each table has an RX part and a TX part
(see Table 18).
The tables are labeled 0 through 15 and are in time-slot
order, i.e., table 0 is used when processing data for
time slot 0. Time-slot number can vary between 0 and
15 and is used in conjunction with the card address to
provide up to 64 time-slot positions on the PCM bus
(see Table 3).
Agere Systems Inc.
(continued)
The DSP Engine ac Path Coefficient Table
The microprocessor interface can control the DSP
coefficients, shown in Table 4. The DSP engine RAM
contains space to hold separate sets of coefficients for
each channel, labeled channel_0 through channel_15.
The coefficients are held in channel order, since they
hold information that is channel specific and does not
change with the time slot (see Table 18).
Table 4 shows the ac path coefficient space for
channel_0.
Table 4. DSP Engine RAM Map for Channel_0 ac
rgain_abs_0
tgain_abs_0
rgain_rel_0
tgain_rel_0
bf_coef_0
Reserved
Reserved
Address
RAM
Path Coefficients
absolute gain
absolute gain
Balance filter
relative gain
relative gain
coefficients
Purpose
RX path
RX path
TX path
TX path
—
—
of Words
Number
Codec Chip Set
10
1
1
1
1
1
1
1 (4000 H)
1 (4000 H)
1 (4000 H)
1 (4000 H)
initialized
Initial
Value
Not
—
—
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