cy28445-5 SpectraLinear Inc, cy28445-5 Datasheet - Page 14

• Manufacturer Part Number: cy28445-5
• Description: Clock Generator For Intel Calistoga Chipset
• Manufacturer: SpectraLinear Inc

Rev 1.1, June 30, 2007
Crystal Loading
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, the total capacitance
the crystal will see must be considered to calculate the appro-
priate capacitive loading (CL).
Figure 1 shows a typical crystal configuration using the two
trim capacitors. An important clarification for the following
discussion is that the trim capacitors are in series with the
crystal not parallel. It’s a common misconception that load
capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is not true.
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
Figure 1. Crystal Capacitive Clarification
SRCC(free running)
SRCT(free running)
SRCT(stoppable)
SRCT(stoppable)
CLKREQ#X
Figure 3. CLK_REQ# Deassertion/Assertion Waveform
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
CL....................................................Crystal load capacitance
CLe......................................... Actual loading seen by crystal
using standard value trim capacitors
Ce..................................................... External trim capacitors
Cs .............................................. Stray capacitance (terraced)
Ci ...........................................................Internal capacitance
(lead frame, bond wires etc.)
CLKREQ# Description
The CLKREQ# signals are active LOW inputs used for clean
enabling and disabling selected SRC outputs. The outputs
controlled by CLKREQ# are determined by the settings in
register byte 8. The CLKREQ# signal is a de-bounced signal
in that it’s state must remain unchanged during two consec-
utive rising edges of SRCC to be recognized as a valid
assertion or deassertion. (The assertion and deassertion of
this signal is absolutely asynchronous.).
CLe
Cs1
Total Capacitance (as seen by the crystal)
=
Figure 2. Crystal Loading Example
Ce1
(
Load Capacitance (each side)
Ce1 + Cs1 + Ci1
X1
C i1
Ce = 2 * CL – (Cs + Ci)
C lock C hip
1
XTAL
Ci2
+
X2
1
C e2
Ce2 + Cs2 + Ci2
CY28445-5
Cs2
1
Page 14 of 26
3 to 6p
33 pF
Pin
Trim
2.8 pF
Trace
)