cy28445-5 SpectraLinear Inc, cy28445-5 Datasheet - Page 3

• Manufacturer Part Number: cy28445-5
• Description: Clock Generator For Intel Calistoga Chipset
• Manufacturer: SpectraLinear Inc

Rev 1.1, June 30, 2007
Pin Descriptions
Table 1. Frequency Select Table FSA, FSB and FSC
Frequency Select Pins (FSA, FSB, and FSC)
Host clock frequency selection is achieved by applying the
appropriate logic levels to FSA, FSB, FSC inputs prior to
VTT_PWRGD# assertion (as seen by the clock synthesizer).
Upon VTT_PWRGD# being sampled low by the clock chip
(indicating processor VTT voltage is stable), the clock chip
samples the FSA, FSB, and FSC input values. For all logic
levels of FSA, FSB, and FSC, VTT_PWRGD# employs a
one-shot functionality in that once a valid low on
VTT_PWRGD# has been sampled, all further VTT_PWRGD#,
FSA, FSB, and FSC transitions will be ignored, except in test
mode.
53
54
55
56
57, 58, 63, 64 PCI[1:4]
61, 67
62, 66
65
68
FSC
1
0
0
0
Pin No.
FSB
0
0
1
1
REF1/FCTSEL0
REF0/FSC
CPU_STP#
PCI_STP#
VDD_PCI
VSS_PCI
PCI5/FCTSEL1
PCIF0/ITP_SEL
FSA
1
1
1
0
(continued)
Name
100 MHz
133 MHz
166 MHz
200 MHz
CPU
I/O, SE
I/O, SE 33 MHz clock output / 3.3V LVTTL input to enable SRC[T/C]10 or
O, SE
O, SE 33 MHz clock outputs.
PWR 3.3V power supply
I, PU
I, PU
GND
100 MHz
100 MHz
100 MHz
100 MHz
Type
PD
PD
I/O
SRC
Fixed 14.318 MHz clock output / 3.3V LVTTL input for selecting for pin 6, 7
(DOT96[T/C], 27M-non-spread and Spread) and pin 10,11 (SRC[T/C]0 or
100M[T/C]_SST) (sampled on the VTT_PWRGD# assertion).
Fixed 14.318 MHz clock output / 3.3V-tolerant input for CPU frequency
selection.
Refer to DC Electrical Specification Table for VilFS_C, VimFS_C and VihFS_C
specifications
3.3V LVTTL input for CPU_STP# active LOW.
3.3V LVTTL input for PCI_STP# active LOW.
Ground
33 MHz clock output / 3.3V LVTTL input for selecting for pin 6, 7
(DOT96[T/C], 27M-non-spread and Spread) and pin10,11 (SRC[T/C]0 or
100M[T/C]_SST) (sampled on the VTT_PWRGD# assertion).
CPU[T/C]2_ITP on pin 36, 37. (sampled on the VTT_PWRGD# assertion).
0 = SRC10 (default)
1 = CPU2_ITP,
FCTSEL1 FCTSEL0 PIN 6
FCTSEL1 FCTSEL0 PIN 6
0
0
1
1
0
0
1
1
PCIF/PCI
33 MHz
33 MHz
33 MHz
33 MHz
0
1
0
1
0
1
0
1
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initialize to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
DOT96T
DOT96T
27M_non spread 27M_Spread SRCT0
OFF Low
DOT96T
DOT96T
27M_non spread 27M_Spread SRCT0
OFF Low
27 MHz
27 MHz
27 MHz
27 MHz
27MHz
Description
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
REF0
PIN 7
DOT96C
DOT96C
TBD
PIN 7
DOT96C
DOT96C
TBD
PIN 10
100MT_SST 100MC_SST
SRCT0
SRCT0
PIN 10
100MT_SST 100MC_SST
SRCT0
SRCT0
96 MHz
96 MHz
96 MHz
96 MHz
DOT96
CY28445-5
Page 3 of 26
PIN 11
SRCC0
SRCC0
SRCC0
PIN 11
SRCC0
SRCC0
SRCC0
48 MHz
48 MHz
48 MHz
48 MHz
USB