cy28445-5 SpectraLinear Inc, cy28445-5 Datasheet - Page 2

• Manufacturer Part Number: cy28445-5
• Description: Clock Generator For Intel Calistoga Chipset
• Manufacturer: SpectraLinear Inc

Rev 1.1, June 30, 2007
Pin Descriptions
1
2
3
4
5
6, 7
8
9, 20, 25, 34,
59, 60
10, 11
12, 17, 28, 35 VDD_SRC
13,14, 15,
16, 18, 19,
21, 22, 23,
24, 26, 27,
29, 30, 32,
33,
31
36, 37
38
39
40
41, 42, 44, 45 CPU[T/C][0:1]
43
46
47
48
49
50
51
Pin No.
PCIF1
VTT_PWRGD#/PD
VDD48
FSA/48M
VSS48
DOT96T/27M_non
spread
DOT96C/27M_Spread
FSB
CLKREQ#[1], [3:6], [8]
SRC[T/C]0/
LCD100M[T/C]
SRC[T/C][1:8]
VSS_SRC
CPUT2_ITP/SRCT10,
CPUC2_ITP/SRCC10
VDDA
VSSA
IREF
VDD_CPU
VSS_CPU
SCLK
SDATA
VDD_REF
XOUT
XIN
Name
I/O, OD SMBus-compatible SDATA.
O, DIF Fixed 96 MHz differential clock output / Single ended 27 MHz clock outputs.
O, DIF 100 MHz differential serial reference clock outputs.
O, DIF Selectable differential CPU / SRC clock output.
O, DIF Differential CPU clock outputs.
O, SE 33 MHz clock output
O,DIF 100 MHz differential serial reference clock output / 100 MHz LVDS differ-
O, SE 14.318 MHz crystal output.
PWR 3.3V power supply.
PWR 3.3V power supply
PWR 3.3V power supply for PLL.
PWR 3.3V power supply
PWR 3.3V power supply
I, PD
GND
I, PU
GND
GND
GND
Type
I/O
I
I
I
I
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS[C:A],
ITP_SEL, FCTSEL[1:0], SEL_CLKREQ#. After VTT_PWRGD# (active LOW)
assertion, this pin becomes a real-time input for asserting power-down (active
HIGH).
3.3V-tolerant input for CPU frequency selection / Fixed 48 MHz clock output.
Refer to DC Electrical Specification Table for Vil_FS and Vih_FS specifications.
Ground.
When configured for 27 MHz, only the clock on pin 7contains spread.
Selected via FCTSEL[0:1] at VTT_PWRGD# assertion.
3.3V-tolerant input for CPU frequency selection.
Refer to DC Electrical Specification Table for Vil_FS and Vih_FS specifications
3.3V LVTTL input for enabling assigned SRC clock (active LOW)
ential clock output.
Selected via FCTSEL[0:1] at VTT_PWRGD# assertion
Ground.
ITP_EN = 0 @ VTT_PWRGD# assertion = SRC10 (default)
ITP_EN = 1@ VTT_PWRGD# assertion =CPU2_ITP
Ground for PLL.
A precision resistor is attached to this pin, which is connected to the internal
current reference.
Ground
SMBus-compatible SCLOCK.
14.318 MHz crystal input.
Description
CY28445-5
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