cy28445-5 SpectraLinear Inc, cy28445-5 Datasheet - Page 16

• Manufacturer Part Number: cy28445-5
• Description: Clock Generator For Intel Calistoga Chipset
• Manufacturer: SpectraLinear Inc

Rev 1.1, June 30, 2007
CPU_STP# Assertion
The CPU_STP# signal is an active low input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
When the CPU_STP# pin is asserted, all CPU outputs that are
set with the SMBus configuration to be stoppable via assertion
CPU_STP# Deassertion
The deassertion of the CPU_STP# signal will cause all CPU
outputs that were stopped to resume normal operation in a
CPUC Internal
CPUT Internal
CPU_STP#
CPU_STP#
CPUT
CPUC
CPUT
CPUC
CPUC, 133MHz
CPUT, 133MHz
SRCC 100MHz
SRCT 100MHz
USB, 48MHz
PCI, 33MHz
DOT96C
DOT96T
REF
PD
Figure 7. CPU_STP# Deassertion Waveform
Figure 5. PD Deassertion Timing Waveform
Figure 6. CPU_STP# Assertion Waveform
Tdrive_CPU_STP#, 10 ns >200 mV
<300 盜, > 200 mV
Tdrive_PWRDN#
<1.8 ms
Tstable
of CPU_STP# will be stopped within two–six CPU clock
periods after being sampled by two rising edges of the internal
CPUC clock. The final states of the stopped CPU signals are
CPUT = HIGH and CPUC = LOW. There is no change to the
output drive current values during the stopped state. The
CPUT is driven HIGH with a current value equal to 6 x (Iref),
and the CPUC signal will be Tri-stated.
synchronous manner. Synchronous manner meaning that no
short or stretched clock pulses will be produce when the clock
resumes. The maximum latency from the deassertion to active
outputs is no more than two CPU clock cycles.
CY28445-5
Page 16 of 26