cy28445-5 SpectraLinear Inc, cy28445-5 Datasheet - Page 9

• Manufacturer Part Number: cy28445-5
• Description: Clock Generator For Intel Calistoga Chipset
• Manufacturer: SpectraLinear Inc

Rev 1.1, June 30, 2007
Byte 9: Control Register 9
Byte 10: Control Register 10
Byte 11: Control Register 11
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
Bit
Bit
Bit
@Pup
@Pup
@Pup
HW
HW
HW
0
0
0
0
1
1
1
0
1
1
1
1
0
0
0
0
0
0
S3
S2
S1
S0
RESERVED
27_M Spread
27M_SS / LCD100M SS
Enable
PCIF1
SRC[T/C]10
RESERVED
RESERVED
SRC[T/C]8
RESERVED
SRC[T/C]10
RESERVED
SRC[T/C]8
RESERVED
RESERVED
RESERVED
RESERVED
27M spread and
non-spread output drive
strength
Name
Name
Name
27_96_100_SSC Spread Spectrum Selection table:
S[3:0] SS%
‘0000’ = –0.45%(Default value)
‘0001’ = –0.9%
‘0010’ = –1.45%
‘0011’ = –1.9%
‘0100’ = ±0.225%
‘0101’ = ±0.45%
‘0110’ = ±0.725%
‘0111’ = ±0.95%
‘1000’ = –0.34%
‘1001’ = –0.68%
‘1010’ = –1.09%
‘1011’ = –1.425%
‘1100’ = ±0.17%
‘1101’ = ±0.34%
‘1110’ = ±0.545%
‘1111’ = ±0.712%
RESERVED, Set = 1
27_MHz Spread Output Enable
0 = Disable (Hi-Z), 1 = Enable.
27M_SS / LCD100M Spread Spectrum Enable.
0 = Disable, 1 = Enable.
33-MHz Output Drive Strength
0 = Low, 1 = High
SRC[T/C]10 Output Enable
0 = Disable (Hi-Z), 1 = Enable
RESERVED
RESERVED
SRC[T/C]8 Output Enable
0 = Disable (Hi-Z), 1 = Enable
RESERVED
Allow control of SRC[T/C]10 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
RESERVED
Allow control of SRC[T/C]8 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
RESERVED Set = 0
RESERVED
RESERVED
RESERVED
27M (Spread and Non-spread) Output Drive Strength
0 = Low, 1 = High
Description
Description
Description
CY28445-5
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