cy28445-5 SpectraLinear Inc, cy28445-5 Datasheet - Page 5

• Manufacturer Part Number: cy28445-5
• Description: Clock Generator For Intel Calistoga Chipset
• Manufacturer: SpectraLinear Inc

Rev 1.1, June 30, 2007
Table 4. Byte Read and Byte Write Protocol
Control Registers
Byte 0: Control Register 0
Byte 1: Control Register 1
27:20
18:11
Bit
Bit
8:2
Bit
10
19
28
29
5
4
3
1
9
7
6
5
4
3
2
1
0
7
6
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Data byte – 8 bits
Acknowledge from slave
Stop
@Pup
@Pup
1
1
1
1
1
1
1
1
1
1
1
1
1
Byte Write Protocol
SRC[T/C]7
SRC[T/C]6
SRC[T/C]5
SRC[T/C]4
SRC[T/C]3
SRC[T/C]2
SRC[T/C]1
SRC[T/C]0
/LCD100M[T/C]
PCIF0
27M_nss / DOT_96[T/C] 27M_nss and DOT_96 MHz Output Enable
USB_48MHz
REF0
REF1
Description
Name
Name
SRC[T/C]7 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]6 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]5 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]4 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]3 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]2 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]1 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]0 /LCD100M[T/C] Output Enable
0 = Disable (Hi-Z), 1 = Enable
PCIF0 Output Enable
0 = Disabled, 1 = Enabled
0 = Disable (Tri-state), 1 = Enabled
USB_48M MHz Output Enable
0 = Disabled, 1 = Enabled
REF0 Output Enable
0 = Disabled, 1 = Enabled
REF1 Output Enable
0 = Disabled, 1 = Enabled
18:11
27:21
37:30
8:2
Bit
10
19
20
28
29
38
39
1
9
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Repeated start
Slave address – 7 bits
Read
Acknowledge from slave
Data from slave – 8 bits
NOT Acknowledge
Stop
Description
Description
Byte Read Protocol
Description
CY28445-5
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