ds21ft40 Maxim Integrated Products, Inc., ds21ft40 Datasheet - Page 32

• Manufacturer Part Number: ds21ft40
• Description: Ds21ft40 Four X Three 12 Channel E1 Framer
• Manufacturer: Maxim Integrated Products, Inc.

CCR5: COMMON CONTROL REGISTER 5 (Address = AA Hex)
CCR6: COMMON CONTROL REGISTER 6 (Address=1D Hex)
(MSB)
(MSB)
SYMBOLS
SYMBOLS
RESALGN
TESALGN
–
–
RCM4
RCM3
RCM2
RCM1
RCM0
–
–
–
–
–
–
RESALGN
–
POSITION
POSITION
CCR5.7
CCR5.6
CCR5.5
CCR5.4
CCR5.3
CCR5.2
CCR5.1
CCR5.0
CCR6.7
CCR6.6
CCR6.5
CCR6.4
CCR6.3
TESALGN
–
NAME AND DESCRIPTION
Not Assigned. Should be set to zero when written
Receive Elastic Store Align. Setting this bit from a zero to a
Receive Channel Monitor Bit 0. LSB of the channel decode.
NAME AND DESCRIPTION
Not Assigned. Should be set to zero when written
Not Assigned. Should be set to zero when written
Not Assigned. Should be set to zero when written
Not Assigned. Should be set to zero when written
Not Assigned. Should be set to zero when written
one may force the receive elastic store’s write/read pointers to
a minimum separation of half a frame. No action will be taken
if the pointer separation is already greater or equal to half a
frame. If pointer separation is less then half a frame, the
command will be executed and data will be disrupted. Should
be toggled after RSYSCLK has been applied and is stable.
Must be cleared and set again for a subsequent align. See
Section 12 for details.
Transmit Elastic Store Align. Setting this bit from a zero to a
one may force the transmit elastic store’s write/read pointers to
a minimum separation of half a frame. No action will be taken
if the pointer separation is already greater or equal to half a
frame. If pointer separation is less then half a frame, the
command will be executed and data will be disrupted. Should
be toggled after TSYSCLK has been applied and is stable.
Must be cleared and set again for a subsequent align. See
Section 12 for details.
Receive Channel Monitor Bit 4. MSB of a channel decode that
determines which receive channel data will appear in the
RDS0M register. See Section 8 for details.
Receive Channel Monitor Bit 3.
Receive Channel Monitor Bit 2.
Receive Channel Monitor Bit 1.
RCM4
–
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RCM3
–
TCLKSRC
RCM2
RCM1
RESR
RCM0
(LSB)
(LSB)
TESR
DS21FT40