ds21ft40 Maxim Integrated Products, Inc., ds21ft40 Datasheet - Page 34

• Manufacturer Part Number: ds21ft40
• Description: Ds21ft40 Four X Three 12 Channel E1 Framer
• Manufacturer: Maxim Integrated Products, Inc.

The SSR register operates differently than the other three. It is a read only register and it reports the status
of the synchronizer in real time. This register is not latched and it is not necessary to precede a read of
this register with a write.
The SR1, SR2, and HSR registers have the unique ability to initiate a hardware interrupt via the INT*
output pin. Each of the alarms and events in the SR1, SR2, and HSR can be either masked or unmasked
from the interrupt pin via the Interrupt Mask Register 1 (IMR1), Interrupt Mask Register 2 (IMR2), and
HDLC Interrupt Mask Register (HIMR) respectively. The HIMR register is covered in Section 14.
The interrupts caused by four of the alarms in SR1 (namely RUA1, RRA, RCL, and RLOS) act differently
than the interrupts caused by other alarms and events in SR1 and SR2 (namely RSA1, RDMA, RSA0,
RSLIP, RMF, RAF, TMF, SEC, TAF, LOTC, RCMF, and TSLIP). These four alarm interrupts will force
the INT* pin low whenever the alarm changes state (i.e., the alarm goes active or inactive according to the
set/clear criteria in Table 6-1). The INT* pin will be allowed to return high (if no other interrupts are
present) when the user reads the alarm bit that caused the interrupt to occur. If the alarm is still present,
the register bit will remain set.
The event caused interrupts will force the INT* pin low when the event occurs. The INT* pin will be
allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the
interrupt to occur.
ISR: INTERRUPT STATUS REGISTER
(Any address from 0C0 Hex to 0FF Hex)
F3HDLC
(MSB)
SYMBOLS
F3HDLC
F2HDLC
F1HDLC
F0HDLC
F3SR
F2SR
F1SR
F3SR
POSITION
ISR.7
ISR.6
ISR.5
ISR.4
ISR.3
ISR.2
ISR.1
F2HDLC
NAME AND DESCRIPTION
FRAMER 3 HDLC CONTROLLER INTERRUPT REQUEST.
0 = No interrupt request pending.
1 = Interrupt request pending.
FRAMER 3 SR1 or SR2 INTERRUPT REQUEST.
0 = No interrupt request pending.
1 = Interrupt request pending.
FRAMER 2 HDLC CONTROLLER INTERRUPT REQUEST.
0 = No interrupt request pending.
1 = Interrupt request pending.
FRAMER 2 SR1 or SR2 INTERRUPT REQUEST.
0 = No interrupt request pending.
1 = Interrupt request pending.
FRAMER 1 HDLC CONTROLLER INTERRUPT REQUEST.
0 = No interrupt request pending.
1 = Interrupt request pending.
FRAMER 1 SR1 or SR2 INTERRUPT REQUEST.
0 = No interrupt request pending.
1 = Interrupt request pending.
FRAMER 0 HDLC CONTROLLER INTERRUPT REQUEST.
0 = No interrupt request pending.
F2SR
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F1HDLC
F1SR
F0HDLC
(LSB)
F0SR
DS21FT40