ds21ft40 Maxim Integrated Products, Inc., ds21ft40 Datasheet - Page 56

• Manufacturer Part Number: ds21ft40
• Description: Ds21ft40 Four X Three 12 Channel E1 Framer
• Manufacturer: Maxim Integrated Products, Inc.

HDLC CONTROLLER REGISTER LIST Table 14-1
HDLC Control Register (HCR)
HDLC Status Register (HSR)
HDLC Interrupt Mask Register (HIMR)
Receive HDLC Information Register
(RHIR)
Receive HDLC FIFO Register (RHFR)
Receive HDLC DS0 Control Register 1
(RDC1)
Receive HDLC DS0 Control Register 2
(RDC2)
Transmit HDLC Information Register
(THIR)
Transmit BOC Register (TBOC)
Transmit HDLC FIFO Register (THFR)
Transmit HDLC DS0 Control Register 1
(TDC1)
Transmit HDLC DS0 Control Register 2
(TDC2)
14.2 HDLC STATUS REGISTERS
Three of the HDLC controller registers (HSR, RHIR, and THIR) provide status information. When a
particular event has occurred (or is occurring), the appropriate bit in one of these three registers will be set
to a one. Some of the bits in these three status registers are latched and some are real time bits that are not
latched. Section 14.4 contains register descriptions that list which bits are latched and which are not.
With the latched bits, when an event occurs and a bit is set to a one, it will remain set until the user reads
that bit. The bit will be cleared when it is read and it will not be set again until the event has occurred
again. The real time bits report the current instantaneous conditions that are occurring and the history of
these bits is not latched.
NAME
general control over the HDLC and BOC
controllers
key status information for both transmit and
receive directions
allows/stops status bits to/from causing an
interrupt
status information on receive HDLC
controller
access to 64–byte HDLC FIFO in receive
direction
controls the HDLC function when used on
DS0 channels
status information on transmit HDLC
controller
enables/disables transmission of BOC codes
access to 64–byte HDLC FIFO in transmit
direction
controls the HDLC function when used on
DS0 channels
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FUNCTION
DS21FT40