ds21ft40 Maxim Integrated Products, Inc., ds21ft40 Datasheet - Page 48

• Manufacturer Part Number: ds21ft40
• Description: Ds21ft40 Four X Three 12 Channel E1 Framer
• Manufacturer: Maxim Integrated Products, Inc.

This method allows the same 8–bit code to be placed into any of the 32 E1 channels. If this method is
used, then the CCR3.5 control bit must be set to zero.
Each of the bit position in the Transmit Idle Registers (TIR1/TIR2/TIR3/TIR4) represent a DS0 channel
in the outgoing frame. When these bits are set to a one, the corresponding channel will transmit the Idle
Code contained in the Transmit Idle Definition Register (TIDR).
The Transmit Idle Registers (TIRs) have an alternate function that allows them to define a Per–Channel
LoopBack (PCLB). If the TIRFS control bit (CCR3.5) is set to one, then the TIRs will determine which
channels (if any) from the backplane should be replaced with the data from the receive side or in other
words, off of the E1 line. If this mode is enabled, then transmit and receive clocks and frame syncs must
be synchronized.
TIR1/TIR2/TIR3: TRANSMIT IDLE REGISTERS (Address=26 to 29 Hex)
[Also used for Per–Channel Loopback]
NOTE:
If CCR3.5=1, then a zero in the TIRs implies that channel data is to be sourced from TSER and a one
implies that channel data is to be sourced from the output of the receive side framer (i.e., Per–Channel
Loopback; see Figure 1–2).
TIDR: TRANSMIT IDLE DEFINITION REGISTER (Address=2A Hex)
10.1.2
The second method involves using the Transmit Channel Control Registers (TCC1/2/3/4) to determine
which of the 32 E1 channels should be overwritten with the code placed in the Transmit Channel
Registers (TC1 to TC32). This method is more flexible than the first in that it allows a different 8–bit
code to be placed into each of the 32 E1 channels.
(MSB)
CH16
CH24
CH32
TIDR7
CH8
(MSB)
SYMBOLS
SYMBOLS
CH1 - 32
TIDR7
TIDR0
CH15
CH23
CH31
CH7
Per–Channel Code Insertion
TIDR6
POSITIONS
TIR1.0 - 4.7
POSITION
CH14
CH22
CH30
CH6
TIDR.7
TIDR.0
TIDR5
CH13
CH21
CH29
CH5
NAME AND DESCRIPTION
Transmit Idle Code Insertion Control Bits.
0 = do not insert the Idle Code in the TIDR into this channel
1 = insert the Idle Code in the TIDR into this channel
NAME AND DESCRIPTION
MSB of the Idle Code (this bit is transmitted first)
LSB of the Idle Code (this bit is transmitted last)
TIDR4
CH12
CH20
CH28
CH4
48 of 87
TIDR3
CH11
CH19
CH27
CH3
TIDR2
CH10
CH18
CH26
CH2
TIDR1
(LSB)
CH17
CH25
CH1
CH9
TIR1 (26)
TIR2 (27)
TIR3 (28)
TIR4 (29)
TIDR0
(LSB)
DS21FT40