ds21ft40 Maxim Integrated Products, Inc., ds21ft40 Datasheet - Page 33

• Manufacturer Part Number: ds21ft40
• Description: Ds21ft40 Four X Three 12 Channel E1 Framer
• Manufacturer: Maxim Integrated Products, Inc.

6. STATUS AND INFORMATION REGISTERS
There is a set of seven registers per framer that contain information on the current real time status of a
framer in the DS21FT40, Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Register
(RIR), Synchronizer status Register (SSR) and a set of three registers for the onboard HDLC controller.
The specific details on the four registers pertaining to the HDLC controller are covered in Section 14 but
they operate the same as the other status registers in the DS21FT40 and this operation is described below.
When a particular event has occurred (or is occurring), the appropriate bit in one of these four registers
will be set to a one. All of the bits in SR1, SR2, and RIR1 registers operate in a latched fashion. The
Synchronizer status Register contents are not latched. This means that if an event or an alarm occurs and
a bit is set to a one in any of the registers, it will remain set until the user reads that bit. The bit will be
cleared when it is read and it will not be set again until the event has occurred again (or in the case of the
RSA1, RSA0, RDMA, RUA1, RRA, RCL, and RLOS alarms, the bit will remain set if the alarm is still
present).
The user will always precede a read of any of the SR1, SR2 and RIR registers with a write. The byte
written to the register will inform the framer which bits the user wishes to read and have cleared. The
user will write a byte to one of these registers, with a one in the bit positions he or she wishes to read and
a zero in the bit positions he or she does not wish to obtain the latest information on. When a one is
written to a bit location, the read register will be updated with the latest information. When a zero is
written to a bit position, the read register will not be updated and the previous value will be held. A write
to the status and information registers will be immediately followed by a read of the same register. The
read result should be logically AND’ed with the mask byte that was just written and this value should be
written back into the same register to insure that bit does indeed clear. This second write step is necessary
because the alarms and events in the status registers occur asynchronously in respect to their access via
the parallel port. This write–read– write scheme allows an external microcontroller or microprocessor to
individually poll certain bits without disturbing the other bits in the register. This operation is key in
controlling the DS21FT40 with higher–order software languages.
SYMBOLS
TCLKSRC
RESR
TESR
POSITION
CCR6.2
CCR6.1
CCR6.0
NAME AND DESCRIPTION
Transmit Clock Source Select. This function allows the user to
Receive Elastic Store Reset. Setting this bit from a zero to a
internally select RCLK as the clock source for the transmit side
formatter.
0 = Transmit side formatter clocked with signal applied at
TCLK pin. LOTC Mux function is operational (TCR1.7)
1 = Transmit side formatter clocked with RCLK.
one will force the receive elastic store to a depth of one frame.
Receive data is lost during the reset. Should be toggled after
RSYSCLK has been applied and is stable. Do not leave this
bit set high.
Transmit Elastic Store Reset. Setting this bit from a zero to a
one will force the transmit elastic store to a depth of one frame.
Transmit data is lost during the reset. Should be toggled after
TSYSCLK has been applied and is stable. Do not leave this
bit set high.
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