ds21ft40 Maxim Integrated Products, Inc., ds21ft40 Datasheet - Page 59

• Manufacturer Part Number: ds21ft40
• Description: Ds21ft40 Four X Three 12 Channel E1 Framer
• Manufacturer: Maxim Integrated Products, Inc.

HSR: HDLC STATUS REGISTER (Address=B1 Hex)
NOTE:
The RPE, RPS, and TMEND bits are latched and will be cleared when read.
HIMR: HDLC INTERRUPT MASK REGISTER (Address=B2 Hex)
(MSB)
(MSB)
SYMBOLS
SYMBOLS
TMEND
–
–
RHALF
THALF
RNE
RPE
TNF
RPE
RPS
RPS
–
–
RPE
RPE
POSITION
POSITION
HIMR.7
HIMR.6
HIMR.5
HSR.7
HSR.6
HSR.5
HSR.4
HSR.3
HSR.2
HSR.1
HSR.0
RPS
RPS
NAME AND DESCRIPTION
Not Assigned. Should be set to zero.
Receive Packet End. Set when the HDLC controller detects
Receive FIFO Half Full. Set when the receive 64–byte FIFO
Receive FIFO Not Empty. Set when the receive 64–byte FIFO
Transmit Message End. Set when the transmit HDLC
NAME AND DESCRIPTION
either the finish of a valid message (i.e., CRC check complete)
or when the controller has experienced a message fault such as
a CRC checking error, or an overrun condition, or an abort has
been seen. The setting of this bit prompts the user to read the
RHIR register for details.
Receive Packet Start. Set when the HDLC controller detects
an opening byte. The setting of this bit prompts the user to
read the RHIR register for details.
fills beyond the half way point. The setting of this bit prompts
the user to read the RHIR register for details.
has at least one byte available for a read. The setting of this bit
prompts the user to read the RHIR register for details.
Transmit FIFO Half Empty. Set when the transmit 64–byte
FIFO empties beyond the half way point. The setting of this
bit prompts the user to read the THIR register for details.
Transmit FIFO Not Full. Set when the transmit 64–byte FIFO
has at least one byte available. The setting of this bit prompts
the user to read the THIR register for details.
controller has finished sending a message. The setting of this
bit prompts the user to read the THIR register for details.
Not Assigned. Should be set to zero.
Receive Packet End.
0 = interrupt masked.
1 = interrupt enabled.
Receive Packet Start.
0 = interrupt masked.
1 = interrupt enabled.
RHALF
RHALF
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RNE
RNE
THALF
THALF
TNF
TNF
TMEND
TMEND
(LSB)
(LSB)
DS21FT40