ds21ft40 Maxim Integrated Products, Inc., ds21ft40 Datasheet - Page 61
ds21ft40
Manufacturer Part Number
ds21ft40
Description
Ds21ft40 Four X Three 12 Channel E1 Framer
Manufacturer
Maxim Integrated Products, Inc.
Datasheet
1.DS21FT40.pdf
(87 pages)
- Current page: 61 of 87
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RHFR: RECEIVE HDLC FIFO REGISTER (Address=B4 Hex)
THIR: TRANSMIT HDLC INFORMATION REGISTER (Address=B6 Hex)
NOTE:
The UDR bit is latched and will be cleared when read.
HDLC7
(MSB)
(MSB)
SYMBOLS
SYMBOLS
TEMPTY
–
HDLC7
HDLC6
HDLC5
HDLC4
HDLC3
HDLC2
HDLC1
HDLC0
TFULL
UDR
–
–
–
–
–
HDLC6
–
POSITION
POSITION
RHFR.7
RHFR.6
RHFR.5
RHFR.4
RHFR.3
RHFR.2
RHFR.1
RHFR.0
THIR.7
THIR.6
THIR.5
THIR.4
THIR.3
THIR.2
THIR.1
THIR.0
HDLC5
–
NAME AND DESCRIPTION
NAME AND DESCRIPTION
HDLC Data Bit 7. MSB of a HDLC packet data byte.
HDLC Data Bit 6.
HDLC Data Bit 5.
HDLC Data Bit 4.
HDLC Data Bit 3.
HDLC Data Bit 2.
HDLC Data Bit 1.
HDLC Data Bit 0. LSB of a HDLC packet data byte.
Not Assigned. Could be any value when read.
Not Assigned. Could be any value when read.
Not Assigned. Could be any value when read.
Not Assigned. Could be any value when read.
Not Assigned. Could be any value when read.
Transmit FIFO Empty. A real–time bit that is set high when
the FIFO is empty.
Transmit FIFO Full. A real–time bit that is set high when the
FIFO is full.
Underrun. Set when the transmit FIFO unwantedly empties
out and an abort is automatically sent.
HDLC4
–
61 of 87
HDLC3
–
EMPTY
HDLC2
HDLC1
TFULL
HDLC0
(LSB)
(LSB)
UDR
DS21FT40
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