ds21ft40 Maxim Integrated Products, Inc., ds21ft40 Datasheet - Page 6

• Manufacturer Part Number: ds21ft40
• Description: Ds21ft40 Four X Three 12 Channel E1 Framer
• Manufacturer: Maxim Integrated Products, Inc.

DESCRIPTION.......................................................................................................................................................................... 1
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2.
3.
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6.
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10.
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9.1
9.2
10.1
10.2
12.1
12.2
13.1
13.2
14.1
14.2
14.3
14.4
DS21FT40 PIN DESCRIPTION....................................................................................................................................... 8
DS21FT44 PIN FUNCTION DESCRIPTION............................................................................................................... 16
DS21FT40 REGISTER MAP.......................................................................................................................................... 19
PARALLEL PORT.......................................................................................................................................................... 24
CONTROL, ID AND TEST REGISTERS..................................................................................................................... 24
STATUS AND INFORMATION REGISTERS ............................................................................................................ 33
ERROR COUNT REGISTERS ...................................................................................................................................... 39
DS0 MONITORING FUNCTION.................................................................................................................................. 41
SIGNALING OPERATION............................................................................................................................................ 44
10.1.1
10.1.2
PER–CHANNEL CODE GENERATION AND LOOPBACK................................................................................ 47
CLOCK BLOCKING REGISTERS .......................................................................................................................... 50
ELASTIC STORES OPERATION ............................................................................................................................ 50
ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION ................................................................ 51
INTERLEAVED PCM BUS OPERATION .............................................................................................................. 64
TIMING DIAGRAMS................................................................................................................................................. 67
DS21FT40 MECHANICAL DIMENSIONS.............................................................................................................. 86
HDLC CONTROLLER FOR THE SA BITS OR DS0............................................................................................. 55
OPERATING PARAMETERS................................................................................................................................... 75
PROCESSOR BASED SIGNALING ........................................................................................................................ 44
HARDWARE BASED SIGNALING ........................................................................................................................ 47
TRANSMIT SIDE CODE GENERATION............................................................................................................... 47
RECEIVE SIDE CODE GENERATION .................................................................................................................. 49
RECEIVE SIDE......................................................................................................................................................... 51
TRANSMIT SIDE ..................................................................................................................................................... 51
INTERNAL REGISTER SCHEME BASED ON DOUBLE–FRAME ..................................................................... 51
INTERNAL REGISTER SCHEME BASED ON CRC4 MULTIFRAME................................................................ 53
G
HDLC S
B
HDLC R
ASIC
ENERAL
Simple Idle Code Insertion and Per–Channel Loopback................................................................................... 47
Per–Channel Code Insertion ............................................................................................................................. 48
O
PERATION
TATUS
EGISTER
O
VERVIEW
R
EGISTERS
D
D
ESCRIPTION
ETAILS
.................................................................................................................................................. 55
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TABLE OF CONTENTS
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DS21FT40