ds21ft40 Maxim Integrated Products, Inc., ds21ft40 Datasheet - Page 57

• Manufacturer Part Number: ds21ft40
• Description: Ds21ft40 Four X Three 12 Channel E1 Framer
• Manufacturer: Maxim Integrated Products, Inc.

Like the other status registers in the framer, the user will always proceed a read of any of the three
registers with a write. The byte written to the register will inform the framer which of the latched bits the
user wishes to read and have cleared (the real time bits are not affected by writing to the status register).
The user will write a byte to one of these registers, with a one in the bit positions he or she wishes to read
and a zero in the bit positions he or she does not wish to obtain the latest information on. When a one is
written to a bit location, the read register will be updated with current value and it will be cleared. When
a zero is written to a bit position, the read register will not be updated and the previous value will be held.
A write to the status and information registers will be immediately followed by a read of the same
register. The read result should be logically AND’ed with the mask byte that was just written and this
value should be written back into the same register to insure that bit does indeed clear. This second write
step is necessary because the alarms and events in the status registers occur asynchronously in respect to
their access via the parallel port. This write–read–write (for polled driven access) or write–read (for
interrupt driven access) scheme allows an external microcontroller or microprocessor to individually poll
certain bits without disturbing the other bits in the register. This operation is key in controlling the
DS21FT40 with higher–order software languages.
Like the SR1 and SR2 status registers, the HSR register has the unique ability to initiate a hardware
interrupt via the INT* output pin. Each of the events in the HSR can be either masked or unmasked from
the interrupt pin via the HDLC Interrupt Mask Register (HIMR). Interrupts will force the INT* pin low
when the event occurs. The INT* pin will be allowed to return high (if no other interrupts are present)
when the user reads the event bit that caused the interrupt to occur.
14.3 BASIC OPERATION DETAILS
As a basic guideline for interpreting and sending HDLC messages, the following sequences can be
applied:
Receive a HDLC Message
1. Enable RPS interrupts.
2. Wait for interrupt to occur.
3. Disable RPS interrupt and enable either RPE, RNE, or RHALF interrupt.
4. Read RHIR to obtain REMPTY status.
5. Repeat step 4.
6. Wait for interrupt, skip to step 4.
7. If POK=0, then discard whole packet, if POK=1, accept the packet.
8. Disable RPE, RNE, or RHALF interrupt, enable RPS interrupt and return to step 1.
A. If REMPTY=0, then record OBYTE, CBYTE, and POK bits and then read the FIFO
B. If REMPTY=1, then skip to step 6
A1. If CBYTE=0 then skip to step 5
A2. If CBYTE=1 then skip to step 7
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