ds21ft40 Maxim Integrated Products, Inc., ds21ft40 Datasheet - Page 50

• Manufacturer Part Number: ds21ft40
• Description: Ds21ft40 Four X Three 12 Channel E1 Framer
• Manufacturer: Maxim Integrated Products, Inc.

RCC1/RCC2/RCC3/RCC4: RECEIVE CHANNEL CONTROL REGISTER
(Address = A4 to A7 Hex)
11.
The Receive Channel blocking Registers (RCBR1 / RCBR2 / RCBR3 / RCBR4) and the Transmit
Channel Blocking Registers (TCBR1 / TCBR2 / TCBR3 / TCBR4) control RCHBLK and TCHBLK pins
on the DS21Q44 die, respectively. The RCHBLK and TCHBLK pins are not bonded out on the
DS21FT40 module. However, the Transmit Channel Blocking Registers have an alternate function that is
supported by the module. Via the CCR3.6 bit, the user has the option to use the TCBRs to determine on a
channel by channel basis, which signaling bits are to be inserted via the TSRs and which are to be sourced
from the TSER. If CCR3.6=1, then a zero in the TCBRs implies that signaling data is to be sourced from
and a one implies that signaling data for that channel is to be sourced from the Transmit Signaling (TS)
registers. See definition below. See the timing in Section 16 for an example. The Receive Channel
Blocking Registers provide no function for the DS21FT40 and should be cleared to zero.
TCBR1/TCBR2/TCBR3/TCBR4: DEFINITION WHEN CCR3.6=1
*=CH1 and CH17 should be set to one to allow the internal TS1 register to create the CAS Multiframe
Alignment Word and Spare/Remote Alarm bits.
12.
Each framer in the DS21FT40 contains dual two–frame (512 bits) elastic stores, one for the receive
direction, and one for the transmit direction. These elastic stores have two main purposes. First, they can
be used to rate convert the E1 data stream to 1.544 Mbps (or a multiple of 1.544 Mbps) which is the T1
rate. Secondly, they can be used to absorb the differences in frequency and phase between the E1 data
stream and an asynchronous (i.e., not frequency locked) backplane clock which can be 1.544 MHz or
2.048 MHz. The backplane clock can burst at rates up to 8.192 MHz. Both elastic stores contain full
controlled slip capability which is necessary for this second purpose. Both elastic stores within a framer
are fully independent and no restrictions apply to the sourcing of the various clocks that are applied to
them. The transmit side elastic store can be enabled whether the receive elastic store is enabled or
(MSB)
(MSB)
CH16
CH24
CH32
CH20
CH24
CH28
CH32
CH8
SYMBOLS
CH1 - 32
CLOCK BLOCKING REGISTERS
ELASTIC STORES OPERATION
CH12
CH16
CH15
CH23
CH31
CH4
CH8
CH7
RCC1.0 - 4.7
POSITION
CH19
CH23
CH27
CH31
CH14
CH22
CH30
CH6
CH11
CH15
CH13
CH21
CH29
CH3
CH7
CH5
NAME AND DESCRIPTION
Receive Code Insertion Control Bits
0 = do not insert data from the RC register into the receive data
stream
1 = insert data from the RC register into the receive data
stream
CH18
CH22
CH26
CH30
CH12
CH20
CH28
CH4
50 of 87
CH10
CH14
CH6
CH11
CH19
CH27
CH2
CH3
CH17*
CH21
CH25
CH29
CH10
CH18
CH26
CH2
(LSB)
CH1*
CH13
CH5
CH9
(LSB)
CH17
CH25
CH1
CH9
TCBR1 (22)
TCBR2 (23)
TCBR3 (24)
TCBR4 (25)
RCC1 (A4)
RCC2 (A5)
RCC3 (A6)
RCC4 (A7)
DS21FT40