ds21ft40 Maxim Integrated Products, Inc., ds21ft40 Datasheet - Page 51

• Manufacturer Part Number: ds21ft40
• Description: Ds21ft40 Four X Three 12 Channel E1 Framer
• Manufacturer: Maxim Integrated Products, Inc.

DS21FT40
disabled and vice versa. Also, each elastic store can interface to either a 1.544 MHz or 2.048 MHz
backplane without regard to the backplane rate the other elastic store is interfacing.
Two mechanisms are available to the user for resetting the elastic stores. The Elastic Store Reset
(CCR6.0 & CCR6.1) function forces the elastic stores to a depth of one frame unconditionally. Data is
lost during the reset. The second method, the Elastic Store Align ( CCR5.5 & CCR5.6) forces the elastic
store depth to a minimum depth of half a frame only if the current pointer separation is already less then
half a frame. If a realignment occurs data is lost. In both mechanisms, independent resets are provided
for both the receive and transmit elastic stores.
12.1 RECEIVE SIDE
If the receive side elastic store is enabled (RCR2.1=1), then the user must provide either a 1.544 MHz
(RCR2.2 =0) or 2.048 MHz (RCR2.2=1) clock at the RSYSCLK pin. The user has the option of either
providing a frame/multiframe sync at the RSYNC pin (RCR1.5=1) or having the RSYNC pin provide a
pulse on frame/multiframe boundaries (RCR1.5=0). If the user wishes to obtain pulses at the frame
boundary, then RCR1.6 must be set to zero and if the user wishes to have pulses occur at the multiframe
boundary, then RCR1.6 must be set to one. If the elastic store is enabled, then either CAS (RCR1.7=0) or
CRC4 (RCR1.7=1) multiframe boundaries will be indicated via the RMSYNC output. If the user selects
to apply a 1.544 MHz clock to the RSYSCLK pin, then every fourth channel of the received E1 data will
be deleted and a F–bit position (which will be forced to one) will be inserted. Hence Channels 1, 5, 9, 13,
17, 21, 25, and 29 (timeslots 0, 4, 8, 12, 16, 20, 24, and 28) will be deleted from the received E1 data
stream). See Section 16 for timing details. If the 512–bit elastic buffer either fills or empties, a controlled
slip will occur. If the buffer empties, then a full frame of data (256–bits) will be repeated at RSER and
the SR1.4 and RIR.3 bits will be set to a one. If the buffer fills, then a full frame of data will be deleted
and the SR1.4 and RIR.4 bits will be set to a one.
12.2 TRANSMIT SIDE
The operation of the transmit elastic store is very similar to the receive side. The transmit side elastic
store is enabled via CCR3.7. A 1.544 MHz (CCR3.1=0) or 2.048 MHz (CCR3.1=1) clock can be applied
to the TSYSCLK input. The TSYSCLK can be a bursty clock with rates up to 8.192 MHz. If the user
selects to apply a 1.544 MHz clock to the TSYSCLK pin, then the data sampled at TSER will be ignored
every fourth channel. Hence Channels 1, 5, 9, 13, 17, 21, 25, and 29 (timeslots 0, 4, 8, 12, 16, 20, 24, and
28) will be ignored. The user must supply a 8 kHz frame sync pulse to the TSSYNC input. See Section
16 for timing details. Controlled slips in the transmit elastic store are reported in the SR2.0 bit and the
direction of the slip is reported in the RIR.6 and RIR.7 bits.
13.
ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION
Each framer in the DS21FT40 provides for access to both the Sa and the Si bits via two different
methods. The first method involves using the internal RAF/RNAF and TAF/TNAF registers and is
discussed in Section 13.1. The second method, which is covered in Section 13.2, involves an expanded
version of the first method.
13.1 INTERNAL REGISTER SCHEME BASED ON DOUBLE–FRAME
On the receive side, the RAF and RNAF registers will always report the data as it received in the
Additional and International bit locations. The RAF and RNAF registers are updated with the setting of
the Receive Align Frame bit in Status Register 2 (SR2.6). The host can use the SR2.6 bit to know when
to read the RAF and RNAF registers. It has 250 us to retrieve the data before it is lost.
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