pi7c8154b Pericom Semiconductor Corporation, pi7c8154b Datasheet
pi7c8154b
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pi7c8154b Summary of contents
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... PI7C8154B Asynchronous 2-Port PCI-to-PCI Bridge st 3545 North 1 Street, San Jose, CA 95134 Telephone: 1-877-PERICOM, (1-877-737-4266) Internet: http://www.pericom.com REVISION 1.12 Fax: 408-435-1100 ...
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... No license is granted by implication or otherwise under any patent, patent rights or other rights, of Pericom Semiconductor Corporation. All other trademarks are of their respective companies. 06-0008 ASYNCHRONOUS 2-PORT Page 2 of 111 MARCH 2006 REVISION 1.12 PI7C8154B PCI-to-PCI BRIDGE ...
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... Corrected ambient temperature maximum rating to -40°C to 85°C (from 0°C to 85°C) in section 17.1 Removed ‘Advance Information’ from headings Removed ‘solutions@pericom.com’ link Corrected unit measure for TGH in section 17.7 from Page 3 of 111 PI7C8154B ASYNCHRONOUS 2-PORT PCI-to-PCI BRIDGE MARCH 2006 REVISION 1.12 ...
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... This page intentionally left blank. 06-0008 ASYNCHRONOUS 2-PORT Page 4 of 111 MARCH 2006 REVISION 1.12 PI7C8154B PCI-to-PCI BRIDGE ...
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... TYPE 0 ACCESS TO PI7C8154A ..................................................................................................32 2.8.2 TYPE 1 TO TYPE 0 CONFIGURATION .......................................................................................32 2.8.3 TYPE 1 TO TYPE 1 FORWARDING .............................................................................................34 2.8.4 SPECIAL CYCLES.........................................................................................................................34 2.9 64-BIT OPERATION.........................................................................................................................35 2.9.1 64-BIT AND 32-BIT TRANSACTIONS INITIATED BY PI7C8154B .............................................35 2.9.2 64-BIT TRANSACTIONS – ADDRESS PHASE .............................................................................35 2.9.3 64-BIT TRANSACTIONS – DATA PHASE ....................................................................................36 2.9.4 64-BIT TRANSACTIONS – RECEIVED BY PI7C8154B ...............................................................36 2.9.5 64-BIT TRANSACTIONS – SUPPORT DURING RESET..............................................................37 06-0008 ...
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... MASTER TERMINATION INITIATED BY PI7C8154B............................................................38 2.11.2 MASTER ABORT RECEIVED BY PI7C8154B .........................................................................38 2.11.3 TARGET TERMINATION RECEIVED BY PI7C8154B............................................................39 2.11.3.1 DELAYED WRITE TARGET TERMINATION RESPONSE ......................................................39 2.11.3.2 POSTED WRITE TARGET TERMINATION RESPONSE.........................................................40 2.11.3.3 DELAYED READ TARGET TERMINATION RESPONSE .......................................................40 2.11.4 TARGET TERMINATION INITIATED BY PI7C8154B ............................................................41 2.11.4.1 TARGET RETRY .......................................................................................................................41 2.11.4.2 TARGET DISCONNECT...........................................................................................................42 2.11.4.3 TARGET ABORT.......................................................................................................................43 3 ADDRESS DECODING ............................................................................................................................43 3.1 ADDRESS RANGES .........................................................................................................................43 3.2 I/O ADDRESS DECODING ...
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... PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS REGISTER – OFFSET 28h82 14.1.23 PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS REGISTER – OFFSET 2Ch 82 14.1.24 I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h .........................................82 14.1.25 I/O LIMIT ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h........................................82 06-0008 ASYNCHRONOUS 2-PORT Page 7 of 111 MARCH 2006 REVISION 1.12 PI7C8154B PCI-to-PCI BRIDGE ...
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... ABNORMAL TERMINATION (INITIATED BY BRIDGE MASTER) ..........................................99 15.2.1 MASTER ABORT ......................................................................................................................99 15.2.2 PARITY AND ERROR REPORTING ........................................................................................99 15.2.3 REPORTING PARITY ERRORS .............................................................................................100 15.2.4 SECONDARY IDSEL MAPPING............................................................................................100 16 IEEE 1149.1 COMPATIBLE JTAG CONTROLLER .........................................................................100 16.1 BOUNDARY SCAN ARCHITECTURE.........................................................................................100 06-0008 ASYNCHRONOUS 2-PORT Page 8 of 111 MARCH 2006 REVISION 1.12 PI7C8154B PCI-to-PCI BRIDGE ...
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... PCI SIGNALING TIMING ................................................................................................110 17.6 RESET TIMING...............................................................................................................................110 17.7 GPIO TIMING (66MHZ & 33MHZ) ...............................................................................................110 17.8 JTAG TIMING .................................................................................................................................110 17.9 POWER CONSUMPTION ..............................................................................................................111 18 PACKAGE INFORMATION .................................................................................................................111 18.1 304-BALL PBGA PACKAGE DIAGRAM .....................................................................................111 18.2 ORDERING INFORMATION.........................................................................................................111 06-0008 ASYNCHRONOUS 2-PORT Page 9 of 111 MARCH 2006 REVISION 1.12 PI7C8154B PCI-to-PCI BRIDGE ...
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... SECONDARY ARBITER EXAMPLE .............................................................................................65 IGURE F 16-1 TEST ACCESS PORT DIAGRAM...............................................................................................101 IGURE F 17-1 PCI SIGNAL TIMING MEASUREMENT CONDITIONS..........................................................109 IGURE F 18-1 304-BALL PBGA PACKAGE OUTLINE ....................................................................................111 IGURE 06-0008 ASYNCHRONOUS 2-PORT Page 10 of 111 MARCH 2006 REVISION 1.12 PI7C8154B PCI-to-PCI BRIDGE 31 BIT OF OFFSET BIT OF OFFSET H ...
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... PCI Local Bus Specification, Revision 2.2. The PI7C8154B supports synchronous and asynchronous bus transactions between devices on the Primary Bus and the Secondary Buses operating up to 66MHz. For the PI7C8154B-80, the Secondary Bus supports up to 80MHz operation. The primary and secondary buses can also operate in concurrent mode, resulting in added increase in system performance ...
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... The de-assertion of P_FRAME# indicates the final data phase requested by the initiator. Before being tri-stated driven to a de-asserted state for one cycle. Page 12 of 111 PI7C8154B ASYNCHRONOUS 2-PORT PCI-to-PCI BRIDGE MARCH 2006 REVISION 1.12 ...
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... PCI clock cycles before asserting it again. I Primary Grant (Active LOW): When asserted, PI7C8154B can access the primary bus. During idle and P_GNT# asserted, bridge will drive P_AD, P_CBE, and P_PAR to valid logic levels. I Primary RESET (Active LOW): When P_RESET# is active, all PCI signals should be asynchronously tri-stated ...
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... P_AD lines are tri-stated. Devices receive data sample P_PAR64 as an input to check for possible parity errors during 64-bit transactions. When not driven, P_PAR64 is pulled valid logic level through external resistors. Page 14 of 111 MARCH 2006 REVISION 1.12 PI7C8154B PCI-to-PCI BRIDGE ...
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... Once asserted in a data phase not de-asserted until the end of the data phase. Before tri-stated driven to a de-asserted state for one cycle. Page 15 of 111 MARCH 2006 REVISION 1.12 PI7C8154B PCI-to-PCI BRIDGE ...
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... Secondary Grant (Active LOW): PI7C8154B asserts these pins to allow external masters to access the secondary bus. Bridge de-asserts these pins for at least 2 PCI clock cycles before asserting it again. During idle and S_GNT# deasserted, PI7C8154B will drive S_AD, S_CBE, and S_PAR. O Secondary RESET (Active LOW): Asserted when any of the following conditions are met: 1 ...
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... S_ACK64# has the same timing as S_DEVSEL#. When deasserting, S_ACK64# is driven to a deasserted state for 1 cycle and then is sustained by an external pull-up resistor. Type Description I Primary Clock Input: Provides timing for all transactions on the primary interface. Page 17 of 111 MARCH 2006 REVISION 1.12 PI7C8154B PCI-to-PCI BRIDGE ...
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... B2 power state. The secondary clocks are disabled and driven to 0. When this pin is tied LOW, there is no effect on the secondary bus clocks when the bridge enters the power state. HOT Page 18 of 111 MARCH 2006 REVISION 1.12 PI7C8154B PCI-to-PCI BRIDGE ...
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... LOW, bits [31:27] offset DEh are set to 11111 to indicate that the secondary devices are capable of asserting PME#. When this pin is tied HIGH, bits [31:27] offset DEh are set to 00000 to indicate that PI7C8154B does not support the PME# pin. I/O EEPROM Data: Serial data interface to the EEPROM ...
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... D6 VDD TS D8 VSS TS D10 VDD I D12 VSS TS D14 VDD P D16 VSS TS D18 VDD TS D20 S_AD[61] TS D22 S_AD[55 Page 20 of 111 MARCH 2006 REVISION 1.12 PI7C8154B PCI-to-PCI BRIDGE TYPE STS STS STS ...
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... R4 BPCCE - R20 P_VIO I R22 CONFIG66 VSS I T4 VDD - T20 VDD TS T22 P_AD[32 P_AD[31 P_AD[30] Page 21 of 111 MARCH 2006 REVISION 1.12 PI7C8154B PCI-to-PCI BRIDGE TYPE ...
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... VDD P AC4 VSS STS AC6 P_STOP# STS AC8 VDD TS AC10 P_AD[10] TS AC12 VDD P AC14 P_REQ64# TS AC16 VDD P AC18 P_AD[57] Page 22 of 111 MARCH 2006 REVISION 1.12 PI7C8154B PCI-to-PCI BRIDGE TYPE ...
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... Memory Write and Invalidate As indicated in Table 2-1, the following PCI commands are not supported by PI7C8154B: PI7C8154B never initiates a PCI transaction with a reserved command code and target, PI7C8154B ignores reserved command codes. PI7C8154B does not generate interrupt acknowledge transactions. PI7C8154B ignores interrupt acknowledge transactions as a target ...
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... The PCI-to-PCI Bridge Architecture Specification supports the use of dual address transactions in the prefetchable memory range only. See Section 3.3.3 for a discussion of prefetchable address space. The PI7C8154B supports dual address transactions in both the upstream and the downstream direction. The PI7C8154B supports a programmable 64-bit address range in prefetchable memory for downstream forwarding of dual address transactions ...
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... DWORD of data. Under this condition, PI7C8154B accepts write data without obtaining access to the target bus. The PI7C8154B can accept one DWORD of write data every PCI clock cycle. That is, no target wait state is inserted. The write data is stored in an internal posted write buffers and is subsequently delivered to the target ...
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... The PI7C8154B initiates the transaction on the target bus. PI7C8154B transfers the write data to the target. If PI7C8154B receives a target retry in response to the write transaction on the target bus, it continues to repeat the write transaction until the data transfer is completed, or until an error condition is encountered ...
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... HIGH), the corresponding byte of write data is not compared. If the initiator repeats the write transaction before the data has been transferred to the target, PI7C8154B returns a target retry to the initiator. PI7C8154B continues to return a target retry to the initiator until write data is delivered to the target, or until an error condition is encountered. When the write transaction is repeated, PI7C8154B does not make a new entry into the delayed transaction queue ...
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... The amount of data that is prefetched depends on the type of transaction. The amount of prefetching may also be affected by the amount of free buffer space available in PI7C8154B, and by any read address boundaries encountered. Prefetching should not be used for those read transactions that have side effects in the target device, that is, control and status registers, FIFO’ ...
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... PI7C8154B stops pre-fetched data, unless the target signals a target disconnect before the read prefetched boundary is reached. When PI7C8154B finishes transferring this read data to the initiator, it returns a target disconnect with the last data transfer, unless the initiator completes the transaction before all pre-fetched read data is delivered ...
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... PI7C8154B drives the captured byte enable bits during the next cycle. If the transaction is a prefetchable read transaction, it drives all byte enable bits to zero for all data phases. If PI7C8154B receives a target retry in response to the read transaction on the target bus, it continues to repeat the read transaction until at least one data transfer is completed, or until an error condition is encountered ...
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... PI7C8154B discards the read transaction and read data from its queues. PI7C8154B also conditionally asserts P_SERR# (see Section 5.4). PI7C8154B has the capability to post multiple delayed read requests maximum of four in each direction initiator starts a read transaction that matches the address and read command of a read transaction that is already queued, the current read command is not posted already contained in the delayed transaction queue ...
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... PCI device that resides on a PCI bus other than the one where the Type 1 transaction is generated. PI7C8154B performs a Type 1 to Type 0 translation when the Type 1 transaction is generated on the primary bus and is intended for a device attached directly to the secondary bus. PI7C8154B must convert the configuration command to a Type 0 format so that the secondary bus device can respond to it. Type 1 to Type 0 translations are performed only in the downstream direction ...
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... PI7C8154B can assert unique address lines to be used as IDSEL signals for devices on the secondary bus, for device numbers ranging from 0 through 8. Because of electrical loading constraints of the PCI bus, more than 16 IDSEL signals should not be necessary. However, if device numbers greater than 16 are desired, some external method of generating IDSEL lines must be used, and no upper address bits are then asserted ...
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... Special cycle transactions can be generated from Type 1 configuration write transactions in either the upstream or the down-stream direction. PI7C8154B initiates a special cycle on the target bus when a Type 1 configuration write transaction is being detected on the initiating bus and the following conditions are met during the address phase: The lowest two address bits on AD[1:0] are equal to 01b ...
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... Once the transaction is completed on the target bus, through detection of the master abort condition, PI7C8154B responds with TRDY# to the next attempt of the con-figuration transaction from the initiator. If more than one data transfer is requested, PI7C8154B responds with a target disconnect operation during the first data phase. ...
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... PI7C8154B is responding to a configuration transaction Only 1 DWORD of data was read from the target If PI7C8154B is the target of a 64-bit memory write transaction able to accept 64 bits of data during each data phase. If PI7C8154B is the target of a memory read transaction, it delivers 64 bits of read data during each data phase and drives PAR64 corresponding to AD[63:32] and CBE[7:4] for each data phase ...
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... If P_REQ64# is HIGH, PI7C8154B knows that the 64-bit extension signals are not connected so it always drives the 64-bit extension outputs to have valid logic levels on the inputs. PI7C8154B will then treat all transactions on the primary as 32-bit. If P_REQ64# is LOW, the 64-bit signals should be connected to pull-up resistors on the board and PI7C8154B does not perform any input biasing ...
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... MASTER TERMINATION INITIATED BY PI7C8154B PI7C8154B initiator, uses normal termination if DEVSEL# is returned by target within five clock cycles of PI7C8154B’s assertion of FRAME# on the target bus initiator, PI7C8154B terminates a transaction when the following conditions are met: During a delayed write transaction, a single DWORD is delivered. ...
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... PI7C8154B asserts P_SERR# if the master-abort-on-posted-write is not set. The master-abort-on- posted-write bit is bit 4 of the P_SERR# event disable register (offset 64h). Note: When PI7C8154B performs a Type 1 to special cycle conversion, a master abort is the expected termination for the special cycle on the target bus. In this case, the master abort received bit is not set, and the Type 1 configuration transaction is disconnected after the first data phase ...
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... DWORD. If the initial write transaction is Memory-Write-and-Invalidate transaction, and a partial delivery of write data to the target is performed before a target disconnect is received, PI7C8154B will use the memory write command to deliver the rest of the write data because an incomplete cache line will be transferred in the subsequent write transaction attempt. ...
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... TARGET RETRY PI7C8154B returns a target retry to the initiator when it cannot accept write data or return read data as a result of internal conditions. PI7C8154B returns a target retry to an initiator when any of the following conditions is met: FOR DELAYED WRITE TRANSACTIONS: The transaction is being entered into the delayed transaction queue ...
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... Otherwise, the transaction is discarded from the buffers. 2.11.4.2 TARGET DISCONNECT PI7C8154B returns a target disconnect to an initiator when one of the following conditions is met: PI7C8154B hits an internal address boundary. PI7C8154B cannot accept any more write data. PI7C8154B has no more read data to deliver. ...
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... TARGET ABORT PI7C8154B returns a target abort to an initiator when one of the following conditions is met: PI7C8154B is returning a target abort from the intended target. When PI7C8154B returns a target abort to the initiator, it sets the signaled target abort bit in the status register corresponding to the initiator interface. 3 ADDRESS DECODING PI7C8154B uses three address ranges that control I/O and memory transaction forwarding ...
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... The top 4 bits of the 8-bit field define bits [15:12] of the I/O base address. The bottom 4 bits read only indicate that PI7C8154B supports 32-bit I/O addressing. Bits [11:0] of the base address are assumed which naturally aligns the base address to a 4KB boundary. The 16 bits contained in the I/O base upper 16 bits register at configuration offset 30h define AD[31:16] of the I/O base address ...
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... All other I/O transactions initiated on the secondary bus are forwarded upstream only if they fall outside the I/O address range. When the ISA enable bit is set, devices downstream of PI7C8154B can have I/O space mapped into the first 256 bytes of each 1KB chunk below the 64KB boundary, or anywhere in I/O space above the 64KB boundary ...
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... Locations accessed in the prefetchable memory address range must have true memory-like behavior and must not exhibit side effects when read. This means that extra reads to a prefetchable memory location must have no side effects. PI7C8154B pre-fetches for all types of memory read commands in this address space. ...
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... PI7C8154B does not respond to any transactions that fall outside this address range on the primary interface and forwards those transactions upstream from the secondary interface (provided that they do not fall into the memory-mapped I/O range or are not forwarded by the VGA mechanism). ...
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... If the prefetchable memory space on the secondary bus resides entirely in the first 4GB of memory, both upper 32 bit register must be set to 0. PI7C8154B then ignores all dual address cycles initiated on the primary interface and forwards all dual address transactions initiated on the secondary interface upstream. ...
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... I/O space. Note: If both the VGA mode bit and the VGA snoop bit are set, PI7C8154B behaves in the same way as if only the VGA mode bit were set. ...
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... PI7C8154B does not combine separate write transactions into a single write transaction—this optimization is best implemented in the originating master. PI7C8154B does not merge bytes on separate masked write transactions to the same DWORD address—this optimization is also best implemented in the originating master. PI7C8154B does not collapse sequential write transactions to the same address into a single write transaction - the PCI Local Bus Specification does not permit this combining of transactions ...
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... In this case, the read data is traveling in the same direction as the write data, and the initiator of the read transaction is on the same side of PI7C8154B as the target of the write transaction. The posted write transaction must complete to the target before the read data is returned to the initiator ...
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... This chapter provides detailed information about how PI7C8154B handles errors. It also describes error status reporting and error operation disabling. 5.1 ADDRESS PARITY ERRORS PI7C8154B checks address parity for all transactions on both buses, for all address and all bus commands. When PI7C8154B detects an address parity error on the primary interface, the following events occur: 06-0008 ...
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... If the parity error response bit is set in the command register, PI7C8154B does not claim the transaction with P_DEVSEL#; this may allow the transaction to terminate in a master abort. If parity error response bit is not set, PI7C8154B proceeds normally and accepts the transaction directed to or across PI7C8154B. ...
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... PI7C8154B sets the data parity detected bit in the secondary status register, if the secondary interface parity error response bit is set in the bridge control register. PI7C8154B forwards the bad parity with the data back to the initiator on the primary bus. If the data with the bad parity is pre-fetched and is not read by the initiator on the primary bus, the data is discarded and the data with bad parity is not returned to the initiator ...
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... PI7C8154B sets the secondary interface data parity detected bit in the secondary status register, if the secondary parity error response bit is set in the bridge control register. PI7C8154B captures the parity error condition to forward it back to the initiator on the primary bus. Similarly, for upstream transactions, when PI7C8154B is delivering data to the target on the ...
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... Similarly, for upstream delayed write transactions, when the parity error is detected on the initiator bus and PI7C8154B has write status to return, the following events occur: PI7C8154B first asserts S_TRDY# and then asserts S_PERR# two cycles later; if the secondary interface parity-error-response bit is set in the bridge control register (offset 3Ch). ...
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... Table 5-1 shows setting the detected parity error bit in the status register, corresponding to the primary interface. This bit is set when PI7C8154B detects a parity error on the primary interface. Table 5-1 SETTING THE PRIMARY INTERFACE DETECTED PARITY ERROR BIT ...
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... Delayed Write Note: x=don’t care Table 5-2 shows setting the detected parity error bit in the secondary status register, corresponding to the secondary interface. This bit is set when PI7C8154B detects a parity error on the secondary interface. Table 5-2 SETTING THE SECONDARY INTERFACE DETECTED PARITY ERROR BIT ...
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... Delayed Write Note: x=don’t care Table 5-5 shows assertion of P_PERR#. This signal is set under the following conditions: PI7C8154B is either the target of a write transaction or the initiator of a read transaction on the primary bus. The parity-error-response bit must be set in the command register of primary interface. ...
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... PI7C8154B has detected P_PERR# asserted on an upstream posted write transaction or S_PERR# asserted on a downstream posted write transaction. PI7C8154B did not detect the parity error as a target of the posted write transaction. The parity error response bit on the command register and the parity error response bit on the bridge control register must both be set ...
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... For the bridge to assert P_SERR# for any reason, the SERR# enable bit must be set in the command register. Whenever the bridge asserts P_SERR#, PI7C8154B must also set the signaled system error bit in the status register. In compliance with the PCI-to-PCI Bridge Architecture Specification, the bridge asserts P_SERR# when it detects the secondary SERR# input, S_SERR#, asserted and the SERR# forward enable bit is set in the bridge control register ...
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... When the initiator repeats the locked read transaction on the primary bus with the same address, transaction type, and byte enable bits, PI7C8154B transfers the read data back to the initiator, and the lock is then also established on the primary bus. ...
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... The initiator must then de-assert LOCK# at the end of the transaction. The bridge sets the appropriate status bits, flagging the abnormal target termination condition (see Section 2.11). Normal forwarding of unlocked posted and delayed transactions is resumed. 06-0008 ASYNCHRONOUS 2-PORT Page 63 of 111 MARCH 2006 REVISION 1.12 PI7C8154B PCI-to-PCI BRIDGE ...
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... When PI7C8154B receives a target abort or a master abort in response to a locked posted write transaction, PI7C8154B cannot pass back that status to the initiator. PI7C8154B asserts SERR# on the initiator bus when a target abort or a master abort is received during a locked posted write transaction, if the SERR# enable bit is set in the command register. Signal SERR# is asserted for the master abort condition if the master abort mode bit is set in the bridge control register (see Section 5 ...
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... Each bus master, including PI7C8154B, can be configured either the low priority group or the high priority group by setting the corresponding priority bit in the arbiter-control register. The arbiter-control register is located at offset 40h. Each master has a corresponding bit. If the bit is set to 1, the master is assigned to the high priority group. If the bit is set to 0, the master is assigned to the low priority group ...
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... Offset 48h, bit 1, can be set park the secondary bus at PI7C8154B. By default, offset 48h, bit 1, is set the internal arbiter is disabled, PI7C8154B parks the secondary bus only when the reconfigured grant signal, S_REQ#[0], is asserted and the secondary bus is idle ...
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... During secondary interface reset, the GPIO interface can be used to shift in a 16-bit serial stream that serves as a secondary bus clock disable mask. Along with the GPIO[3] pin, a live insertion bit can be used to bring the PI7C8154B to a halt through hardware, permitting live insertion of option cards behind the PI7C8154B. ...
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... SECONDARY CLOCK CONTROL The PI7C8154B uses the GPIO pins and the MSK_IN signal to input a 16-bit serial data stream. This data stream is shifted into the secondary clock control register and is used for selectively disabling secondary clock outputs. The serial data stream is shifted in as soon as P_RESET# is detected deasserted and the secondary reset signal, S_RESET#, is detected asserted ...
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... When live insertion mode is enabled, whenever GPIO[3] is driven to a value of 1, the I/O enable, the memory enable, and the master enable bits are internally masked to 0. This means that target, PI7C8154B no longer accepts any I/O or memory transactions, on either interface. When read, the register bits still reflect the value originally written by a configuration write command ...
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... EEPROM. bit[0]: reserved bit[4:1]: 0000 = stop autoload at offset 03h 0001 = stop autoload at offset 0Fh 0011 = stop autoload at offset 2Bh other combinations are undefined bit[7:5]: reserved ENABLE MISCELLANEOUS FUNCTIONS Page 70 of 111 PI7C8154B ASYNCHRONOUS 2-PORT PCI-to-PCI BRIDGE MARCH 2006 REVISION 1.12 ...
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... PRIMARY AND SECONDARY CLOCK INPUTS PI7C8154B implements a primary clock input for the PCI interface. The primary interface is synchronized to the primary clock input, P_CLK, and the secondary interface is synchronized to the secondary clock input. The secondary clock operates at either the same frequency as the primary clock, at half of the frequency of the primary clock, or can be derived from the secondary clock input (ASYNC_CLKIN) ...
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... One of the secondary clock outputs must be used to feedback to S_CLKIN 11.3 ASYNCHRONOUS MODE To set the PI7C8154B into asynchronous mode, ASYNC_SEL# must be set asynchronous mode, the S_CLKOUT[9:0] outputs will be derived from ASYNC_CLKIN. Clock division is still functional based on the setting of the P_M66EN and S_M66EN pins. For example, when P_M66EN is HIGH and S_M66EN is LOW, the S_CLKOUT[9:0] outputs will be equal to half of the ASYN_CLKIN ...
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... S_CBE[3:0] are driven LOW on the secondary interface and other control signals are tri-stated. PI7C8154B performs a chip reset. Registers that have default values are reset. PI7C8154B samples P_REQ64# to determine whether the 64-bit extension is enabled on the primary. P_RESET# asserting and de-asserting edges can be asynchronous to P_CLK and S_CLKOUT. ...
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... CHIP RESET The chip reset bit in the diagnostic control register can be used to reset the PI7C8154B and the secondary bus. When the chip reset bit is set, all registers and chip state are reset and all signals are tri-stated. ...
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... CONFIGURATION REGISTERS PCI configuration defines a 64 DWORD space to define various attributes of PI7C8154B as shown below. Table 14-1 CONFIGURATION SPACE MAP 31-24 Device ID Primary Status Reserved Secondary Latency Timer Secondary Status Memory Limit Address Prefetchable Memory Limit Address I/O Limit Address Upper 16-bit Bridge Control Arbiter Control ...
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... Read / Write 1 to Set Type Description R/O Identifies Pericom as vendor of this device. Hardwired as 12D8h. Type Description R/O Identifies this device as the PI7C8154B. Hardwired as 8154h. Type Description Controls response to I/O access on the primary interface 0: ignore I/O transactions on the primary interface R/W 1: enable response to I/O transactions on the primary interface Reset to 0 ...
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... No parity error detected on the primary interface (bridge is the primary bus master) 1: Parity error detected on the primary interface (bridge is the primary bus master) Reset to 0 R/O DEVSEL# timing (medium decoding) 01: medium DEVSEL# decoding Reset to 01 Page 77 of 111 PI7C8154B ASYNCHRONOUS 2-PORT PCI-to-PCI BRIDGE MARCH 2006 REVISION 1.12 ...
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... Reset to 0 Type Description R/W This register sets the value for the Master Latency Timer, which starts counting when the master asserts FRAME#. Reset to 0 Page 78 of 111 PI7C8154B ASYNCHRONOUS 2-PORT PCI-to-PCI BRIDGE MARCH 2006 REVISION 1.12 ...
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... Designated in units of PCI bus clocks. Latency timer checks for master accesses on the secondary bus interfaces that remain unclaimed by any target. Reset to 0 Type Description R/O Read as 01h to indicate 32-bit I/O addressing R/O Returns 00 when read. Reset to 00. Page 79 of 111 PI7C8154B ASYNCHRONOUS 2-PORT PCI-to-PCI BRIDGE MARCH 2006 REVISION 1.12 ...
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... R/WC Reset to 0 Set to 1 (by a master) when transactions on its secondary interface are terminated with Master Abort R/WC Reset to 0 Set to 1 when S_SERR# is asserted R/WC Reset to 0 Page 80 of 111 PI7C8154B ASYNCHRONOUS 2-PORT PCI-to-PCI BRIDGE MARCH 2006 REVISION 1.12 ...
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... Defines the bottom address of an address range for the bridge to determine when to forward memory read and write transactions from one interface to the other. The upper 12 bits correspond to address bits [31:20] and are writable. The lower 20 bits are assumed Page 81 of 111 PI7C8154B ASYNCHRONOUS 2-PORT PCI-to-PCI BRIDGE MARCH 2006 REVISION 1.12 ...
Page 82
... Reset to 0 Type Description R/W Defines the upper 16-bits of a 32-bit top address of an address range for the bridge to determine when to forward I/O transactions from one interface to the other. Reset to 0 Page 82 of 111 PI7C8154B ASYNCHRONOUS 2-PORT PCI-to-PCI BRIDGE MARCH 2006 REVISION 1.12 ...
Page 83
... I/O limit registers that are in the first 64KB of I/O space that address the last 768 bytes in each 1KB block. Secondary I/O transactions are forwarded upstream if the address falls within the last 768 bytes in each 1KB block Reset to 0 Page 83 of 111 PI7C8154B ASYNCHRONOUS 2-PORT PCI-to-PCI BRIDGE MARCH 2006 REVISION 1.12 ...
Page 84
... Timer. 1: P_SERR# is asserted on the primary interface as a result of the expiration of either the Primary Discard Timer or the Secondary Discard Timer. Reset to 0 Page 84 of 111 PI7C8154B ASYNCHRONOUS 2-PORT PCI-to-PCI BRIDGE PCI clock cycles. PCI clock cycles. PCI clock cycles. PCI clock cycles. ...
Page 85
... Bits [24:16] correspond to request inputs S_REQ[8:0] 0: low priority 1: high priority Reset to 0 R/W Controls whether the secondary interface of the bridge is in the high priority group or the low priority group. 0: low priority 1: high priority Reset to 1 Page 85 of 111 PI7C8154B ASYNCHRONOUS 2-PORT PCI-to-PCI BRIDGE MARCH 2006 REVISION 1.12 ...
Page 86
... Enable downstream memory read prefetching dynamic control R/W 1: Disable downstream memory read prefetching dynamic control Reset Enable upstream memory read prefetching dynamic control R/W 1: Disable upstream memory read prefetching dynamic control Reset to 0 Page 86 of 111 PI7C8154B ASYNCHRONOUS 2-PORT PCI-to-PCI BRIDGE MARCH 2006 REVISION 1.12 ...
Page 87
... Preemption enabled after 32 clock cycles after FRAME asserted 0111: Preemption enabled after 64 clock cycles after FRAME asserted Type Description Hot Swap switch time slot set to 0003A98h (15K PCI clocks). R/W Reset to 0003A98h. Page 87 of 111 PI7C8154B ASYNCHRONOUS 2-PORT PCI-to-PCI BRIDGE MARCH 2006 REVISION 1.12 ...
Page 88
... Stores the EEPROM word address for the EEPROM cycle. R/W Reset to 0 Type Description Stores the EEPROM data to be written into the EEPROM or receives the R/W data from the EEPROM after an EEPROM read cycle is completed. Page 88 of 111 PI7C8154B ASYNCHRONOUS 2-PORT PCI-to-PCI BRIDGE MARCH 2006 REVISION 1.12 ...
Page 89
... Defines the upper 32-bits of a 64-bit top address of an address range for the bridge to determine when to forward upstream memory read and write R/W transactions. Reset to 0 Type Description R/O Returns 0 when read. Reset to 0 Page 89 of 111 PI7C8154B ASYNCHRONOUS 2-PORT PCI-to-PCI BRIDGE MARCH 2006 REVISION 1.12 ...
Page 90
... P_SERR# is not asserted even though the bridge is not able to transfer and read data from the target after 2 in the command register is set. Reset to 0. R/O Returns 0 when read. Reset to 0. Page 90 of 111 PI7C8154B ASYNCHRONOUS 2-PORT PCI-to-PCI BRIDGE 24 attempts and the SERR# enable bit MARCH 2006 REVISION 1.12 ...
Page 91
... S_CLKOUT[0] 01: enable S_CLKOUT[0] R/W 10: enable S_CLKOUT[0] 11: disable S_CLKOUT[0] and driven HIGH Reset to 00 S_CLKOUT[1] (slot 1) Enable 00: enable S_CLKOUT[1] 01: enable S_CLKOUT[1] R/W 10: enable S_CLKOUT[1] 11: disable S_CLKOUT[1] and driven HIGH Reset to 00 Page 91 of 111 PI7C8154B ASYNCHRONOUS 2-PORT PCI-to-PCI BRIDGE MARCH 2006 REVISION 1.12 ...
Page 92
... S_CLKOUT[4] and driven HIGH R/W This bit is initialized upon secondary reset by shifting in a serial data stream. The bit is assigned to correspond to the Bridge secondary clock input (S_CLKIN). Reset Returns 11 when read. Reset to 11. Page 92 of 111 PI7C8154B ASYNCHRONOUS 2-PORT PCI-to-PCI BRIDGE MARCH 2006 REVISION 1.12 ...
Page 93
... R/W 1: alias MEMRL or MEMRM to MEMR for memory read retry cycles from initiator on the secondary interface Reset to 1 Page 93 of 111 PI7C8154B ASYNCHRONOUS 2-PORT PCI-to-PCI BRIDGE 24 attempts. MARCH 2006 REVISION 1.12 ...
Page 94
... Reset Enable the out of order capability between two DTR requests from two FIFO’s R/W 1: Disable the out of order capability between two DTR requests from two FIFO’s Reset to 0 Page 94 of 111 PI7C8154B ASYNCHRONOUS 2-PORT PCI-to-PCI BRIDGE MARCH 2006 REVISION 1.12 ...
Page 95
... Read as 04h to indicate that these are Slot Indentification registers. R/O Type Description Read as E8h. Points to Vital Products Data register. R/O Type Description Indicates expansion slot number R/W Reset to 0 First in chassis R/W Reset to 0 R/O Returns 0 when read. Reset to 0 Page 95 of 111 PI7C8154B ASYNCHRONOUS 2-PORT PCI-to-PCI BRIDGE PCI clocks. MARCH 2006 REVISION 1.12 ...
Page 96
... D1 state (supported if bit[25] offset DCh is HIGH) 10: D2 state (supported if bit[26] offset DCh is HIGH) 11: D3 state Reset to 0 R/O Read as 0 R/O Read bridge does not support the PME# pin. Page 96 of 111 PI7C8154B ASYNCHRONOUS 2-PORT PCI-to-PCI BRIDGE MARCH 2006 REVISION 1.12 ...
Page 97
... INS is not armed and neither INS nor EXT has a value of 1 R/O 1: either INS or EXT has a value INS is armed Reset LED on R/W 1: LED off Reset to 0 Page 97 of 111 PI7C8154B ASYNCHRONOUS 2-PORT PCI-to-PCI BRIDGE . This bit is HOT MARCH 2006 REVISION 1.12 ...
Page 98
... The least significant byte of this register corresponds to the byte of VPD at the address specified by the VPD address register. The data from or R/W written to this register uses the normal PCI byte transfer capabilities. Reset to 0 Page 98 of 111 PI7C8154B ASYNCHRONOUS 2-PORT PCI-to-PCI BRIDGE MARCH 2006 REVISION 1.12 ...
Page 99
... ABNORMAL TERMINATION (INITIATED BY BRIDGE MASTER) 15.2.1 MASTER ABORT Master abort indicates that when PI7C8154B acts as a master and receives no response (i.e., no target asserts DEVSEL# or S_DEVSEL#) from a target, the bridge deasserts FRAME# and then de-asserts IRDY#. 15.2.2 PARITY AND ERROR REPORTING Parity must be checked for all addresses and write data. Parity is defined on the P_PAR, P_PAR64, S_PAR, and S_PAR64 signals. Parity should be even ( even number of‘ ...
Page 100
... Master Abort. 15.2.4 SECONDARY IDSEL MAPPING When PI7C8154B detects a Type 1 configuration transaction for a device connected to the secondary, it translates the Type 1 transaction to Type 0 transaction on the downstream interface. Type 1 configuration format uses a 5-bit field at P_AD[15:11 device number. This is translated to S_AD[31:16] by PI7C8154B. ...
Page 101
... TAP PINS The PI7C8154B’s TAP pins form a serial port composed of four input connections (TMS, TCK, TRST# and TDI) and one output connection (TDO). These pins are described in Table 16-1. The TAP pins provide access to the instruction register and the test data registers. ...
Page 102
... TAP TEST DATA REGISTERS The PI7C8154B contains two test data registers (bypass and boundary-scan). Each test data register selected by the TAP controller is connected serially between TDI and TDO. TDI is connected to the test data register’s most significant bit. TDO is connected to the least significant bit ...
Page 103
... BOUNDARY SCAN REGISTER The boundary-scan register contains a cell for each pin as well as control cells for I/O and the high- impedance pin. Table 16-2 shows the bit order of the PI7C8154B boundary-scan register. All table cells that contain “Control” select the direction of bi-directional pins or high-impedance output pins. When a “ ...
Page 104
... A14 S_AD[10] B14 S_AD[11] C14 S_AD[12] D13 S_AD[13] A13 S_AD[14] B13 S_AD[15] C13 S_CBE[1] C12 * Page 104 of 111 MARCH 2006 REVISION 1.12 PI7C8154B PCI-to-PCI BRIDGE Type BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR ...
Page 105
... GPIO[3] K2 GPIO[2] K3 GPIO[1] L4 GPIO[0] L1 S_CLKOUT[ S_CLKOUT[1] L3 S_CLKOUT[2] M3 S_CLKOUT[3] M1 S_CLKOUT[4] M2 S_CLKOUT[5] N3 Page 105 of 111 MARCH 2006 REVISION 1.12 PI7C8154B PCI-to-PCI BRIDGE Type BIDIR INPUT BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR CONTROL BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR ...
Page 106
... AB12 P_AD[3] AB13 P_AD[2] AA13 P_AD[1] Y13 P_AD[0] AA14 P_ACK64# AB14 P_REQ64# AC14 P_CBE[7] AA15 Page 106 of 111 MARCH 2006 REVISION 1.12 PI7C8154B PCI-to-PCI BRIDGE Type OUTPUT OUTPUT OUTPUT OUTPUT INPUT INPUT INPUT INPUT CONTROL BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR ...
Page 107
... U23 P_AD[35] U20 P_AD[34] U22 * P_AD[33] T23 P_AD[32] T22 P_PAR64 T21 CONFIG66 R22 MSK_IN R21 Page 107 of 111 MARCH 2006 REVISION 1.12 PI7C8154B PCI-to-PCI BRIDGE Type BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR BIDIR ...
Page 108
... I = 1500μA out out out 0 < V < the input device. DD Page 108 of 111 PI7C8154B ASYNCHRONOUS 2-PORT PCI-to-PCI BRIDGE -65°C to 150°C -40°C to 85°C -0.3V to 3.6V -0.5V to 5.5V 125°C Min. Max. Units Notes 3 3 0.5 ...
Page 109
... P_CLK, S_CLKOUT[9:0] LOW time LOW 06-0008 66 MHz Min. Max. 1,2 1,2 1 1,2 1 Condition 20pF load Page 109 of 111 MARCH 2006 REVISION 1.12 PI7C8154B ASYNCHRONOUS 2-PORT PCI-to-PCI BRIDGE 33 MHz Min. Max Units . 10 Min. Max. Units 0 0.250 3.47 4.20 ...
Page 110
... TDO valid delay from TCK falling edge JD T TDO float delay from TCK falling edge JFD 1. Measured between 0.8V to 2.0V 2. Measured between 2.0V to 0.8V 3. C1=50pF 06-0008 Condition 20pF load Page 110 of 111 PI7C8154B ASYNCHRONOUS 2-PORT PCI-to-PCI BRIDGE Min. Max. Units 0 0.250 3.47 4. Min. ...
Page 111
... Figure 18-1 304-BALL PBGA PACKAGE OUTLINE Thermal characteristics can be found on the web: http://www.pericom.com/packaging/mechanicals.php 18.2 ORDERING INFORMATION Part Number PI7C8154BNA PI7C8154BNAE PI7C8154BNA-80 PI7C8154BNAE-80 PI7C8154BNAI PI7C8154BNAIE 06-0008 Typical 1.38 417 Speed Pin – Package 66MHz 304 – PBGA 66MHz 304 – PBGA (Pb-free & Green) 66MHz (80MHz on the Secondary) 304 – ...