pi7c8154b Pericom Semiconductor Corporation, pi7c8154b Datasheet - Page 39

• Manufacturer Part Number: pi7c8154b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0008
2.11.3
2.11.3.1
transaction with a master abort. This sets the received-master-abort bit in the status register
corresponding to the target bus.
For delayed read and write transactions, PI7C8154B is able to reflect the master abort condition
back to the initiator. When PI7C8154B detects a master abort in response to a delayed transaction,
and when the initiator repeats the transaction, PI7C8154B does not respond to the transaction with
DEVSEL#, which induces the master abort condition back to the initiator. The transaction is then
removed from the delayed transaction queue. When a master abort is received in response to a
posted write transaction, PI7C8154B discards the posted write data and makes no more attempts to
deliver the data. PI7C8154B sets the received-master-abort bit in the status register when the
master abort is received on the primary bus, or it sets the received master abort bit in the secondary
status register when the master abort is received on the secondary interface. When master abort is
detected in posted write transaction with both master-abort-mode bit (bit[5] of bridge control
register) and the SERR# enable bit (bit 8 of command register for secondary bus) are set,
PI7C8154B asserts P_SERR# if the master-abort-on-posted-write is not set. The master-abort-on-
posted-write bit is bit 4 of the P_SERR# event disable register (offset 64h).
Note: When PI7C8154B performs a Type 1 to special cycle conversion, a master abort is the
expected termination for the special cycle on the target bus. In this case, the master abort received
bit is not set, and the Type 1 configuration transaction is disconnected after the first data phase.
TARGET TERMINATION RECEIVED BY PI7C8154B
When PI7C8154B initiates a transaction on the target bus and the target responds with DEVSEL#,
the target can end the transaction with one of the following types
of termination:
PI7C8154B handles these terminations in different ways, depending on the type of transaction
being performed.
DELAYED WRITE TARGET TERMINATION RESPONSE
When PI7C8154B initiates a delayed write transaction, the type of target termination received from
the target can be passed back to the initiator. Table 2-7 shows the response to each type of target
termination that occurs during a delayed write transaction.
PI7C8154B repeats a delayed write transaction until one of the following conditions is met:
PI7C8154B makes 2
retry.
Table 2-7 DELAYED WRITE TARGET TERMINATION RESPONSE
Normal termination (upon de-assertion of FRAME#)
Target retry
Target disconnect
Target abort
PI7C8154B completes at least one data transfer.
PI7C8154B receives a master abort.
PI7C8154B receives a target abort.
24
(default) or 2
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(maximum) write attempts resulting in a response of target
MARCH 2006 REVISION 1.12
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
PI7C8154B