pi7c8154b Pericom Semiconductor Corporation, pi7c8154b Datasheet - Page 68

• Manufacturer Part Number: pi7c8154b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0008
8.2
SECONDARY CLOCK CONTROL
The PI7C8154B uses the GPIO pins and the MSK_IN signal to input a 16-bit serial data stream.
This data stream is shifted into the secondary clock control register and is used for selectively
disabling secondary clock outputs.
The serial data stream is shifted in as soon as P_RESET# is detected deasserted and the secondary
reset signal, S_RESET#, is detected asserted. The deassertion of S_RESET# is delayed until the
PI7C8154B completes shifting in the clock mask data, which takes 23 clock cycles. After that, the
GPIO pins can be used as general-purpose I/O pins.
An external shift register should be used to load and shift the data. The GPIO pins are used for shift
register control and serial data input. Table 8-1 shows the operation of the GPIO pins.
Table 8-1 GPIO OPERATION
The data is input through the dedicated input signal, MSK_IN.
The shift register circuitry is not necessary for correct operation of PI7C8154B. The shift register
can be eliminated, and MSK_IN can be tied LOW to enable all secondary clock outputs or tied
HIGH to force all secondary clock outputs HIGH. Table 8-2 shows the format of the serial stream.
Table 8-2 GPIO SERIAL DATA FORMAT
The first 8 bits contain the PRSNT#[1:0] signal values for four slots, and these bits control the
S_CLKOUT[3:0] outputs. If one or both of the PRSNT#[1:0] signals are 0, that indicates that a
card is present in the slot and therefore the secondary clock for that slot is not masked. If these
clocks are connected to devices and not to slots, one or both of the bits should be tied low to enable
the clock.
The next 5 bits are the clock mask for devices; each bit enables or disables the clock for one device.
These bits control the S_CLKOUT[8:4] outputs: 0 enables the clock, and 1 disables the clock.
GPIO[0]
GPIO[1]
GPIO[2]
GPIO[3]
[1:0]
[3:2]
[5:4]
[7:6]
[10]
[11]
[12]
[13]
[14]
[15]
Bit
[8]
[9]
GPIO Pin
Slot 0 PRSNT#[1:0] or device 0
Slot 1 PRSNT#[1:0] or device 1
Slot 2 PRSNT#[1:0] or device 2
Slot 3 PRSNT#[1:0] or device 3
Device 4
Device 5
Device 6
Device 7
Device 8
PI7C8154B S_CLKIN
Reserved
Reserved
Page 68 of 111
Description
Shift register clock output at 33MHz max frequency
Not used
Shift register control
0: Load
1: Shift
Not used
Operation
MARCH 2006 REVISION 1.12
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
S_CLKOUT
NA
NA
0
1
2
3
4
5
6
7
8
9
PI7C8154B