pi7c8154b Pericom Semiconductor Corporation, pi7c8154b Datasheet - Page 61

• Manufacturer Part Number: pi7c8154b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0008
6
6.1
6.2
In compliance with the PCI-to-PCI Bridge Architecture Specification, the bridge asserts P_SERR#
when it detects the secondary SERR# input, S_SERR#, asserted and the SERR# forward enable bit
is set in the bridge control register. In addition, the bridge also sets the received system error bit in
the secondary status register.
The bridge also conditionally asserts P_SERR# for any of the following reasons:
The device-specific P_SERR# status register reports the reason for the assertion of P_SERR#. Most
of these events have additional device-specific disable bits in the P_SERR# event disable register
that make it possible to mask out P_SERR# assertion for specific events. The master timeout
condition has a SERR# enable bit for that event in the bridge control register and therefore does not
have a device-specific disable bit.
EXCLUSIVE ACCESS
This chapter describes the use of the LOCK# signal to implement exclusive access to a target for
transactions that cross the bridge.
CONCURRENT LOCKS
The primary and secondary bus lock mechanisms operate concurrently except when a locked
transaction crosses the bridge. A primary master can lock a primary target without affecting the
status of the lock on the secondary bus, and vice versa. This means that a primary master can lock a
primary target at the same time that a secondary master locks a secondary target.
ACQUIRING EXCLUSIVE ACCESS ACROSS PI7C8154B
For any PCI bus, before acquiring access to the LOCK# signal and starting a series of locked
transactions, the initiator must first check that both of the following conditions are met:
For the bridge to assert P_SERR# for any reason, the SERR# enable bit must be set in the
command register.
Whenever the bridge asserts P_SERR#, PI7C8154B must also set the signaled system error bit
in the status register.
Target abort detected during posted write transaction.
Master abort detected during posted write transaction.
Posted write data discarded after 2
Parity error reported on target bus during posted write transaction (see previous section)
Delayed write data discarded after 2
Delayed read data cannot be transferred from target after 2
retries received)
Master timeout on delayed transaction
The PCI bus must be idle.
The LOCK# signal must be de-asserted.
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(default) attempts to deliver (2
(default) attempts to deliver (2
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(default) attempts (2
MARCH 2006 REVISION 1.12
ASYNCHRONOUS 2-PORT
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target retries received).
target retries received)
PCI-to-PCI BRIDGE
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PI7C8154B
target