pi7c8154b Pericom Semiconductor Corporation, pi7c8154b Datasheet - Page 81

• Manufacturer Part Number: pi7c8154b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0008
14.1.18
14.1.19
14.1.20
MEMORY BASE REGISTER – OFFSET 20h
MEMORY LIMIT REGISTER – OFFSET 20h
PREFETCHABLE MEMORY BASE ADDRESS REGISTER – OFFSET 24h
Bit
31
Bit
3:0
15:4
Bit
19:16
31:20
Bit
3:0
15:4
Function
Detected Parity
Error
Function
Reserved
Memory Base
Address [15:4]
Function
Reserved
Memory Limit
Address [31:20]
Function
64-bit addressing
Prefetchable
Memory Base
Address [31:20]
Type
R/WC
Type
R/O
R/W
Type
R/O
R/W
Type
R/O
R/W
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Description
Set to 1 when address or data parity error is detected on the secondary
interface
Reset to 0
Description
Lower four bits of register are read only and return 0.
Reset to 0
Defines the bottom address of an address range for the bridge to
determine when to forward memory transactions from one interface to the
other. The upper 12 bits correspond to address bits [31:20] and are
writable. The lower 20 bits corresponding to address bits [19:0] are
assumed to be 0.
Reset to 0
Description
Lower four bits of register are read only and return 0.
Reset to 0
Defines the top address of an address range for the bridge to determine
when to forward memory transactions from one interface to the other.
The upper 12 bits correspond to address bits [31:20] and are writable.
The lower 20 bits corresponding to address bits [19:0] are assumed to be
FFFFFh.
Description
Indicates 64-bit addressing
0000: 32-bit addressing
0001: 64-bit addressing
Reset to 0001
Defines the bottom address of an address range for the bridge to
determine when to forward memory read and write transactions from one
interface to the other. The upper 12 bits correspond to address bits
[31:20] and are writable. The lower 20 bits are assumed to be 0.
MARCH 2006 REVISION 1.12
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
PI7C8154B