pi7c8154b Pericom Semiconductor Corporation, pi7c8154b Datasheet - Page 17

• Manufacturer Part Number: pi7c8154b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0008
1.2.4
1.2.5
SECONDARY BUS INTERFACE SIGNALS – 64-EXTENSTION
CLOCK SIGNALS
Name
S_AD[63:32]
S_CBE[7:4]
S_PAR64
S_REQ64#
S_ACK64#
Name
P_CLK
Pin #
C20, A21, D20, C21, C23,
C22, D21, E20, D22, E21,
E23, F21, F23, F22, G20,
G22, G21, H23, H22, H21,
J23, J20, J22, K23, K22,
K21, L23, L21, L22, M22,
M23, M21
A19, C19, A20, D19
N21
B19
C18
Pin #
T3
Page 17 of 111
Type
Type
STS
STS
TS
TS
TS
I
Description
Secondary Upper 32-bit Address/Data:
Multiplexed address and data bus. Address is
indicated by S_FRAME# assertion. Write data is
stable and valid when S_IRDY# is asserted and read
data is stable and valid when S_IRDY# is asserted.
Data is transferred on rising clock edges when both
S_IRDY# and S_TRDY# are asserted. During bus
idle, bridge drives S_AD to a valid logic level when
S_GNT# is asserted respectively.
Secondary Upper 32-bit Command/Byte
Enables: Multiplexed command field and byte
enable field. During address phase, the initiator
drives the transaction type on these pins. The
initiator then drives the byte enables during data
phases. During bus idle, bridge drives S_CBE[7:0]
to a valid logic level when the internal grant is
asserted.
Secondary Upper 32-bit Parity: S_PAR64 carries
the even parity of S_AD[63:32] and S_CBE[7:4] for
both address and data phases. S_PAR64 is driven
by the initiator and is valid 1 cycle after the first
address phase when a dual address command is used
and S_REQ64# is asserted. S_PAR64 is valid 1
clock cycle after the second address phase of a dual
address transaction when S_REQ64# is asserted.
S_PAR64 is valid 1 cycle after valid data is driven
when both S_REQ64# and S_ACK64# are asserted
for that data phase. S_PAR64 is driven by the
device driving read or write data 1 cycle after the
S_AD lines are driven. S_PAR64 is tri-stated 1
cycle after the S_AD lines are tri-stated. Devices
receive data sample S_PAR64 as an input to check
for possible parity errors during 64-bit transactions.
When not driven, S_PAR64 is pulled up to a valid
logic level through external resistors.
Secondary 64-bit Transfer Request: S_REQ64#
is asserted by the initiator to indicate that the
initiator is requesting a 64-bit data transfer.
S_REQ64# has the same timing as S_FRAME#.
When S_REQ64# is asserted LOW during reset, a
64-bit data path is supported. When S_REQ64# is
HIGH during reset, bridge drives S_AD[63:32],
S_CBE[7:4], and S_PAR64 to valid logic levels.
When deasserting, S_REQ64# is driven to a
deasserted state for 1 cycle and then sustained by an
external pull-up resistor.
Secondary 64-bit Transfer Acknowledge:
S_ACK64# is asserted by the target only when
S_REQ64# is asserted by the initiator to indicate the
target’s ability to transfer data using 64 bits.
S_ACK64# has the same timing as S_DEVSEL#.
When deasserting, S_ACK64# is driven to a
deasserted state for 1 cycle and then is sustained by
an external pull-up resistor.
Description
Primary Clock Input: Provides timing for all
transactions on the primary interface.
MARCH 2006 REVISION 1.12
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
PI7C8154B