pi7c8154b Pericom Semiconductor Corporation, pi7c8154b Datasheet - Page 48

• Manufacturer Part Number: pi7c8154b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0008
3.4
3.4.1
If the prefetchable memory space on the secondary bus resides entirely in the first 4GB of memory,
both upper 32 bit register must be set to 0. PI7C8154B then ignores all dual address cycles
initiated on the primary interface and forwards all dual address transactions initiated on the
secondary interface upstream.
If the prefetchable memory space on the secondary bus resides entirely above the first 4GB of
memory, both the prefetchable memory base address upper 32 bit register and the prefetchable
memory limit address upper 32 bit register must be initialized to nonzero values. PI7C8154B
ignores all single address memory transactions initiated on the primary and forwards all single
address memory transactions initiated on the secondary upstream, unless the memory falls within
the memory mapped I/O or VGA memory range. A dual address memory transaction is forwarded
downstream from the primary if it falls within the address range defined by the prefetchable
memory base address, prefetchable memory base address upper 32 bits, prefetchable memory limit
address, and prefetchable memory limit address upper 32 bits. If the dual address cycle initiated on
the secondary falls outside this address range, it is forwarded upstream to the primary. PI7C8154B
does not respond to a dual address cycle initiated on the primary that falls outside this address
range, or to a dual address cycle initiated on the secondary that falls within the address range.
If the prefetchable memory space on the secondary bus resides on top of the 4GB boundary, the
prefetchable memory base address upper 32 bit register is set to 0 and the prefetchable memory
limit address upper 32 bit register is initialized to a nonzero value. Single address cycle memory
transactions are compared to the prefetchable memory base address register only. A transaction
initiated on the primary is forwarded downstream if the address is greater than or equal to the base
address. A transaction initiated on the secondary is forwarded upstream if the address is less than
the base address. Dual address cycles are compared to the prefetchable memory limit address and
the prefetchable memory limit address upper 32 bit register. If the address of the dual address
cycle is less than or equal to the limit, the transaction is forwarded downstream from the primary
and is ignored on the secondary. If the address of the dual address cycle is greater than this limit,
the transaction is ignored on the primary and is forwarded upstream from the secondary.
The prefetchable memory base address upper 32 bit register is located at offset 28h of the
configuration register and the prefetchable memory limit address upper 32 bit register is located at
offset 2Ch. Both registers are reset to 0.
VGA SUPPORT
PI7C8154B provides two modes for VGA support:
VGA MODE
When a VGA-compatible device exists downstream from PI7C8154B, set the VGA mode bit in the
bridge control register in configuration space to enable VGA mode. When PI7C8154B is operating
in VGA mode, it forwards downstream those transactions addressing the VGA frame buffer
memory and VGA I/O registers, regardless of the values of the base and limit address registers.
PI7C8154B ignores transactions initiated on the secondary interface addressing these locations.
The VGA frame buffer consists of the following memory address range:
VGA mode, supporting VGA-compatible addressing
VGA snoop mode, supporting VGA palette forwarding
Page 48 of 111
MARCH 2006 REVISION 1.12
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
PI7C8154B