pi7c8154b Pericom Semiconductor Corporation, pi7c8154b Datasheet - Page 16

• Manufacturer Part Number: pi7c8154b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0008
Name
S_TRDY#
S_DEVSEL#
S_STOP#
S_LOCK#
S_PERR#
S_SERR#
S_REQ#[8:0]
S_GNT#[8:0]
S_RESET#
S_M66EN
S_CFN#
Pin #
A10
B10
C10
A11
C11
B11
E1, E3, D2, D1, E4, D3, C2,
C1, D4
H1, G3, G2, G4, G1, F2, F1,
F3, E2
H2
A14
K1
Page 16 of 111
Type
I/OD
STS
STS
STS
STS
STS
TS
O
I
I
I
Description
Secondary TRDY (Active LOW): Driven by the
target of a transaction to indicate its ability to
complete current data phase on the secondary side.
Once asserted in a data phase, it is not de-asserted
until the end of the data phase. Before tri-stated, it is
driven to a de-asserted state for one cycle.
Secondary Device Select (Active LOW): Asserted
by the target indicating that the device is accepting
the transaction. As a master, bridge waits for the
assertion of this signal within 5 cycles of
S_FRAME# assertion; otherwise, terminate with
master abort. Before tri-stated, it is driven to a de-
asserted state for one cycle.
Secondary STOP (Active LOW): Asserted by the
target indicating that the target is requesting the
initiator to stop the current transaction. Before tri-
stated, it is driven to a de-asserted state for one
cycle.
Secondary LOCK (Active LOW): Asserted by an
initiator, one clock cycle after the first address phase
of a transaction, when it is propagating a locked
transaction downstream. Bridge does not propagate
locked transactions upstream.
Secondary Parity Error (Active LOW): Asserted
when a data parity error is detected for data received
on the secondary interface. Before being tri-stated,
it is driven to a de-asserted state for one cycle.
Secondary System Error (Active LOW): Can be
driven LOW by any device to indicate a system
error condition.
Secondary Request (Active LOW): This is
asserted by an external device to indicate that it
wants to start a transaction on the secondary bus.
The input is externally pulled up through a resistor
to VDD.
Secondary Grant (Active LOW): PI7C8154B
asserts these pins to allow external masters to access
the secondary bus. Bridge de-asserts these pins for
at least 2 PCI clock cycles before asserting it again.
During idle and S_GNT# deasserted, PI7C8154B
will drive S_AD, S_CBE, and S_PAR.
Secondary RESET (Active LOW): Asserted when
any of the following conditions are met:
1.
2.
3.
When asserted, all control signals are tri-stated and
zeroes are driven on S_AD, S_CBE, S_PAR, and
S_PAR64.
Secondary Interface 66MHz Operation: This
input is used to specify if bridge is capable of
running at 66MHz on the secondary side. When
HIGH, the Secondary bus may run at 66MHz.
When LOW, the Secondary bus may only run at
33MHz. If P_M66EN is pulled LOW, the
S_M66EN is driven LOW.
Secondary Bus Central Function Control Pin:
When tied LOW, it enables the internal arbiter.
When tied HIGH, an external arbiter must be used.
S_REQ#[0] is reconfigured to be the secondary bus
grant input, and S_GNT#[0] is reconfigured to be
the secondary bus request output.
Signal P_RESET# is asserted.
Secondary reset bit in bridge control register in
configuration space is set.
The chip reset bit in the chip control register in
configuration space is set.
MARCH 2006 REVISION 1.12
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
PI7C8154B