pi7c8154b Pericom Semiconductor Corporation, pi7c8154b Datasheet - Page 63

• Manufacturer Part Number: pi7c8154b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0008
6.2.2
6.3
The first transaction to establish LOCK# must be Memory Read. If the first transaction is not
Memory read, the following transactions behave accordingly:
When the bridge receives a target abort or a master abort in response to the delayed locked read
transaction, this status is passed back to the initiator, and no locks are established on either the
target or the initiator bus. The bridge resumes forwarding unlocked transactions in both directions.
LOCKED TRANSACTION IN UPSTREAM DIRECTION
The bridge ignores upstream lock and transactions. The bridge will pass these transactions as
normal transactions without lock established.
ENDING EXCLUSIVE ACCESS
After the lock has been acquired on both initiator and target buses, the bridge must maintain the
lock on the target bus for any subsequent locked transactions until the initiator relinquishes the
lock.
The only time a target-retry causes the lock to be relinquished is on the first transaction of a locked
sequence. On subsequent transactions in the sequence, the target retry has no effect on the status of
the lock signal.
An established target lock is maintained until the initiator relinquishes the lock. The bridge does
not know whether the current transaction is the last one in a sequence of locked transactions until
the initiator de-asserts the LOCK# signal at end of the transaction.
When the last locked transaction is a delayed transaction, the bridge has already completed the
transaction on the target bus. In this example, as soon as the bridge detects that the initiator has
relinquished the LOCK# signal by sampling it in the de-asserted state while FRAME# is de-
asserted, the bridge de-asserts the LOCK# signal on the target bus as soon as possible. Because of
this behavior, LOCK# may not be de-asserted until several cycles after the last locked transaction
has been completed on the target bus. As soon as the bridge has de-asserted LOCK# to indicate the
end of a sequence of locked transactions, it resumes forwarding unlocked transactions.
When the last locked transaction is a posted write transaction, the bridge de-asserts LOCK# on the
target bus at the end of the transaction because the lock was relinquished at the end of the write
transaction on the initiator bus.
When the bridge receives a target abort or a master abort in response to a locked delayed
transaction, the bridge returns a target abort or a master abort when the initiator repeats the locked
transaction. The initiator must then de-assert LOCK# at the end of the transaction. The bridge sets
the appropriate status bits, flagging the abnormal target termination condition (see Section 2.11).
Normal forwarding of unlocked posted and delayed transactions is resumed.
Type 0 Configuration Read/Write induces master abort.
Type 1 Configuration Read/Write induces master abort.
I/O Read induces master abort.
I/O Write induces master abort.
Memory Write induces master abort.
Page 63 of 111
MARCH 2006 REVISION 1.12
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
PI7C8154B