pi7c8154b Pericom Semiconductor Corporation, pi7c8154b Datasheet - Page 57

• Manufacturer Part Number: pi7c8154b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0008
5.3
During downstream write transactions, when a data parity error is reported on the target
(secondary) bus by the target’s assertion of S_PERR#, the following events occur:
During upstream write transactions, when a data parity error is reported on the target (primary) bus
by the target’s assertion of P_PERR#, the following events occur:
Assertion of P_SERR# is used to signal the parity error condition when the initiator does not know
that the error occurred. Because the data has already been delivered with no errors, there is no other
way to signal this information back to the initiator. If the parity error has forwarded from the
initiating bus to the target bus, P_SERR# will not be asserted.
DATA PARITY ERROR REPORTING
In the previous sections, the responses of the bridge to data parity errors are presented according to
the type of transaction in progress. This section organizes the responses of the bridge to data parity
errors according to the status bits that the bridge sets and the signals that it asserts.
Table 5-1 shows setting the detected parity error bit in the status register, corresponding to the
primary interface. This bit is set when PI7C8154B detects a parity error on the primary interface.
Table 5-1 SETTING THE PRIMARY INTERFACE DETECTED PARITY ERROR BIT
(bit 31 of offset 04h)
Primary Detected
0
0
1
0
1
Parity Error Bit
Bridge sets the data parity detected bit in the status register of secondary interface, if the parity
error response bit is set in the bridge control register of the secondary interface.
Bridge asserts P_SERR# and sets the signaled system error bit in the status register, if all the
following conditions are met:
Bridge sets the data parity detected bit in the status register, if the parity error response bit is
set in the command register of the primary interface.
Bridge asserts P_SERR# and sets the signaled system error bit in the status register, if all the
following conditions are met:
The SERR# enable bit is set in the command register.
The posted write parity error bit of P_SERR# event disable register is not set.
The parity error response bit is set in the bridge control register of the secondary interface.
The parity error response bit is set in the command register of the primary interface.
Bridge has not detected the parity error on the primary (initiator) bus which the parity
error is not forwarded from the primary bus to the secondary bus.
The SERR# enable bit is set in the command register
The parity error response bit is set in the bridge control register of the secondary interface
The parity error response bit is set in the command register of the primary interface
Bridge has not detected the parity error on the secondary (initiator) bus, which the parity
error is not forwarded from the secondary bus to the primary bus
Transaction Type
Read
Read
Read
Read
Posted Write
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Downstream
Downstream
Upstream
Upstream
Downstream
Direction
Primary
Secondary
Primary
Secondary
Primary
Bus Where Error
Was Detected
MARCH 2006 REVISION 1.12
ASYNCHRONOUS 2-PORT
Primary/ Secondary Parity
Error Response Bits
PCI-to-PCI BRIDGE
x / x
x / x
x / x
x / x
x / x
PI7C8154B