pi7c8154b Pericom Semiconductor Corporation, pi7c8154b Datasheet - Page 94

• Manufacturer Part Number: pi7c8154b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0008
Bit
4
5
6
7
8
9
10
11
12
Function
Secondary
Memory Write
Command Alias
Enable
Primary Memory
Read
Line/Multiple
Alias Enable
Secondary
Memory Read
Line/Multiple
Alias Enable
Primary Memory
Write and
Invalidate
Command Alias
Disable
Secondary
Memory Write
and Invalidate
Command Alias
Disable
Enable Long
Request
Enable
Secondary To
Hold Request
Longer
Enable Primary
To Hold Request
Longer
Ordering Rules
Control 1
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Page 94 of 111
Description
0: exact matching for non-posted memory write retry cycles from initiator
on the secondary interface
1: alias MEMWI to MEMW for non-posted memory write retry cycles
from initiator on the secondary interface
Reset to 0
0: Exact matching for memory read line/multiple retry cycles from
initiator on the primary interface
1: alias MEMRL to MEMRM or MEMRM to MEMRL for memory read
retry cycles from initiator on the primary interface
Reset to 1
0: Exact matching for memory read line/multiple retry cycles from
initiator on the secondary interface
1: alias MEMRL to MEMRM or MEMRM to MEMRL for memory read
retry cycles from initiator on the secondary interface
Reset to 1
0: When accepting MEMWI commands on primary, bridge converts
MEMWI to MEMW on destination bus
1: When accepting MEMWI commands on primary, bridge does not
convert MEMWI to MEMW on destination bus
Reset to 0
0: When accepting MEMWI commands on secondary, bridge converts
MEMWI to MEMW on destination bus
1: When accepting MEMWI commands on secondary, bridge does not
convert MEMWI to MEMW on destination bus
Reset to 0
0: normal lock operation
1: enable long request for lock cycle
Reset to 0
0: internal secondary master will release REQ# after FRAME# assertion
1: internal secondary master will hold REQ# until there is no transactions
pending in FIFO or until terminated by target
Reset to 1
0: internal Primary master will release REQ# after FRAME# assertion
1: internal Primary master will hold REQ# until there is no transactions
pending in FIFO or until terminated by target
Reset to 1
0: Enable the out of order capability between two DTR requests from
two FIFO’s
1: Disable the out of order capability between two DTR requests from
two FIFO’s
Reset to 0
MARCH 2006 REVISION 1.12
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
PI7C8154B