pi7c8154b Pericom Semiconductor Corporation, pi7c8154b Datasheet - Page 38

• Manufacturer Part Number: pi7c8154b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0008
2.11.1
2.11.2
the same cycle in which FRAME# deasserts. If FRAME# is already deasserted, IRDY# can be
deasserted on the next clock cycle following detection of the master abort condition.
The target can terminate transactions with one of the following types of termination:
TRDY# and DEVSEL# asserted in conjunction with FRAME# deasserted and IRDY# asserted.
STOP# and DEVSEL# asserted with TRDY# deasserted during the first data phase. No data
transfers occur during the transaction. This transaction must be repeated.
STOP#, DEVSEL# and TRDY# asserted. It signals that this is the last data transfer of the
transaction.
STOP# and DEVSEL# asserted with TRDY# de-asserted after previous data transfers have been
made, indicating that no more data transfers will be made during this transaction.
STOP# asserted with DEVSEL# and TRDY# de-asserted. Indicates that target will never be able to
complete this transaction. DEVSEL# must be asserted for at least one cycle during the transaction
before the target abort is signaled.
MASTER TERMINATION INITIATED BY PI7C8154B
PI7C8154B, as an initiator, uses normal termination if DEVSEL# is returned by target within five
clock cycles of PI7C8154B’s assertion of FRAME# on the target bus. As an initiator, PI7C8154B
terminates a transaction when the following conditions are met:
If PI7C8154B is delivering posted write data when it terminates the transaction because the master
latency timer expires, it initiates another transaction to deliver the remaining write data. The
address of the transaction is updated to reflect the address of the current DWORD to be delivered.
If PI7C8154B is pre-fetching read data when it terminates the transaction because the master
latency timer expires, it does not repeat the transaction to obtain more data.
MASTER ABORT RECEIVED BY PI7C8154B
If the initiator initiates a transaction on the target bus and does not detect DEVSEL# returned by
the target within five clock cycles of the assertion of FRAME#, PI7C8154B terminates the
Normal termination
Target retry
Target disconnect with data transfer
Target disconnect without data transfer
Target abort
During a delayed write transaction, a single DWORD is delivered.
During a non-prefetchable read transaction, a single DWORD is transferred from the target.
During a prefetchable read transaction, a pre-fetch boundary is reached.
For a posted write transaction, all write data for the transaction is transferred from data buffers
to the target.
For burst transfer, with the exception of “Memory Write and Invalidate” transactions, the
master latency timer expires and the PI7C8154B’s bus grant is de-asserted.
The target terminates the transaction with a retry, disconnect, or target abort.
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MARCH 2006 REVISION 1.12
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
PI7C8154B