pi7c8154b Pericom Semiconductor Corporation, pi7c8154b Datasheet - Page 47

• Manufacturer Part Number: pi7c8154b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0008
3.3.3
transactions initiated on the secondary interface that fall into this address range. PI7C8154B does
not respond to any transactions that fall outside this address range on the primary interface and
forwards those transactions upstream from the secondary interface (provided that they do not fall
into the memory-mapped I/O range or are not forwarded by the VGA mechanism).
The prefetchable memory range supports 64-bit addressing and provides additional registers to
define the upper 32 bits of the memory address range, the prefetchable memory base address upper
32 bits register, and the prefetchable memory limit address upper 32 bits register. For address
comparison, a single address cycle (32-bit address) prefetchable memory transaction is treated like
a 64-bit address transaction where the upper 32 bits of the address are equal to 0. This upper 32-bit
value of 0 is compared to the prefetchable memory base address upper 32 bits register and the
prefetchable memory limit address upper 32 bits register. The prefetchable memory base address
upper 32 bits register must be 0 to pass any single address cycle transactions downstream.
Prefetchable memory address range has a granularity and alignment of 1MB. Maximum memory
address range is 4GB when 32-bit addressing is being used. Prefetchable memory address range is
defined by a 16-bit prefetchable memory base address register at configuration offset 24h and by a
16-bit prefetchable memory limit address register at offset 26h. The top 12 bits of each of these
registers correspond to bits [31:20] of the memory address. The lowest 4 bits are hardwired to 1h.
The lowest 20 bits of the prefetchable memory base address are assumed to be 0 0000h, which
results in a natural alignment to a 1MB boundary. The lowest 20 bits of the prefetchable memory
limit address are assumed to be FFFFFh, which results in an alignment to the top of a 1MB block.
Note: The initial state of the prefetchable memory base address register is 0000 0000h. The initial
state of the prefetchable memory limit address register is 000F FFFFh. Note that the initial states of
these registers define a prefetchable memory range at the bottom 1MB block of memory. Write
these registers with their appropriate values before setting either the memory enable bit or the
master enable bit in the command register in configuration space.
To turn off the prefetchable memory address range, write the prefetchable memory base address
register with a value greater than that of the prefetchable memory limit address register. The entire
base value must be greater than the entire limit value, meaning that the upper 32 bits must be
considered. Therefore, to disable the address range, the upper 32 bits registers can both be set to the
same value, while the lower base register is set greater than the lower limit register. Otherwise, the
upper 32-bit base must be greater than the upper 32-bit limit.
PREFETCHABLE MEMORY 64-BIT ADDRESSING REGISTERS
PI7C8154B supports 64-bit memory address decoding for forwarding of dual address memory
transactions. Dual address cycle is used for 64-bit addressing. The first address phase of the dual
address cycle contains the low 32 bits of the address and the second address phase contains the
high 32 bits. The high 32 bits must never be 0 during a dual address cycle.
The prefetchable memory address range is defined by implementing the prefetchable memory base
address upper 32 bits register and the prefetchable memory limit address upper 32 bits register.
The prefetchable address space can be defined as either:
Residing entirely in the first 4GB of memory
Residing entirely above the first 4GB of memory
Crossing the first 4GB memory boundary
Page 47 of 111
MARCH 2006 REVISION 1.12
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
PI7C8154B