pi7c8154b Pericom Semiconductor Corporation, pi7c8154b Datasheet - Page 30

• Manufacturer Part Number: pi7c8154b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0008
2.7.5
2.7.6
placed in the read data queue directed toward the initiator bus interface and is transferred to the
initiator when the initiator repeats the read transaction.
PI7C8154B accepts a delayed read request, by sampling the read address, read bus command, and
address parity. When IRDY# is asserted, PI7C8154B then samples the byte enable bits for the first
data phase. This information is entered into the delayed transaction queue. PI7C8154B terminates
the transaction by signaling a target retry to the initiator. Upon reception of the target retry, the
initiator is required to continue to repeat the same read transaction until at least one data transfer is
completed, or until a target response (target abort or master abort) other than a target retry is
received.
DELAYED READ COMPLETION ON TARGET BUS
When delayed read request reaches the head of the delayed transaction queue, PI7C8154B
arbitrates for the target bus and initiates the read transaction only if all previously queued posted
write transactions have been delivered. PI7C8154B uses the exact read address and read command
captured from the initiator during the initial delayed read request to initiate the read transaction. If
the read transaction is a non-prefetchable read, PI7C8154B drives the captured byte enable bits
during the next cycle. If the transaction is a prefetchable read transaction, it drives all byte enable
bits to zero for all data phases. If PI7C8154B receives a target retry in response to the read
transaction on the target bus, it continues to repeat the read transaction until at least one data
transfer is completed, or until an error condition is encountered. If the transaction is terminated via
normal master termination or target disconnect after at least one data transfer has been completed,
PI7C8154B does not initiate any further attempts to read more data.
If PI7C8154B is unable to obtain read data from the target after 2
attempts, PI7C8154B will report system error. The number of attempts is programmable.
PI7C8154B also asserts P_SERR# if the primary SERR# enable bit is set in the command register.
See Section 5.4 for information on the assertion of P_SERR#.
Once PI7C8154B receives DEVSEL# and TRDY# from the target, it transfers the data read to the
opposite direction read data queue, pointing toward the opposite inter-face, before terminating the
transaction. For example, read data in response to a downstream read transaction initiated on the
primary bus is placed in the upstream read data queue. The PI7C8154B can accept one DWORD of
read data each PCI clock cycle; that is, no master wait states are inserted. The number of
DWORD’s transferred during a delayed read transaction matches the prefetch address boundary
given in Table 2-4 (assuming no disconnect is received from the target).
DELAYED READ COMPLETION ON INITIATOR BUS
When the transaction has been completed on the target bus, and the delayed read data is at the head
of the read data queue, and all ordering constraints with posted write transactions have been
satisfied, the PI7C8154B transfers the data to the initiator when the initiator repeats the transaction.
For memory read transactions, PI7C8154B aliases memory read line and memory read multiple bus
commands to memory read when matching the bus command of the transaction to the bus
command in the delayed transaction queue if bit[3] of offset 74h is set to ‘1’. PI7C8154B returns a
target disconnect along with the transfer of the last DWORD of read data to the initiator. If
PI7C8154B initiator terminates the transaction before all read data has been transferred, the
remaining read data left in data buffers is discarded.
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MARCH 2006 REVISION 1.12
(default) or 2
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
32
(maximum)
PI7C8154B