pi7c8154b Pericom Semiconductor Corporation, pi7c8154b Datasheet - Page 8

• Manufacturer Part Number: pi7c8154b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0008
15
16
15.1
15.2
16.1
14.1.26
14.1.27
14.1.28
14.1.29
14.1.30
14.1.31
14.1.32
14.1.33
14.1.34
14.1.35
14.1.36
14.1.37
14.1.38
14.1.39
14.1.40
14.1.41
14.1.42
14.1.43
14.1.44
14.1.45
14.1.46
14.1.47
14.1.48
14.1.49
14.1.50
14.1.51
14.1.52
14.1.53
14.1.54
14.1.55
14.1.56
14.1.57
14.1.58
14.1.59
14.1.60
14.1.61
14.1.62
14.1.63
14.1.64
14.1.65
14.1.66
BRIDGE BEHAVIOR ...............................................................................................................................99
15.2.1
15.2.2
15.2.3
15.2.4
IEEE 1149.1 COMPATIBLE JTAG CONTROLLER .........................................................................100
5Ch
60h
BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES.....................................................................99
ABNORMAL TERMINATION (INITIATED BY BRIDGE MASTER) ..........................................99
BOUNDARY SCAN ARCHITECTURE.........................................................................................100
CAPABILITY POINTER REGISTER – OFFSET 34h ...............................................................83
INTERRUPT LINE REGISTER – OFFSET 3Ch .......................................................................83
INTERRUPT PIN REGISTER – OFFSET 3Ch .........................................................................83
BRIDGE CONTROL REGISTER – OFFSET 3Ch ....................................................................83
DIAGNOSTIC / CHIP CONTROL REGISTER – OFFSET 40h................................................85
ARBITER CONTROL REGISTER – OFFSET 40h....................................................................85
EXTENDED CHIP CONTROL REGISTER – OFFSET 48h.....................................................86
UPSTREAM MEMORY CONTROL REGISTER – OFFSET 48h..............................................87
SECONDARY BUS ARBITER PREEMPTION CONTROL REGISTER – OFFSET 4Ch..........87
HOT SWAP SWITCH TIME SLOT REGISTER – OFFSET 4Ch...............................................87
EEPROM AUTOLOAD CONTROL / STATUS REGISTER – OFFSET 50h .............................88
EEPROM ADDRESS / CONTROL REGISTER – OFFSET 54h ...............................................88
EEPROM DATA REGISTER – OFFSET 54h ...........................................................................88
UPSTREAM (S TO P) MEMORY BASE ADDRESS REGISTER – OFFSET 58h .....................89
UPSTREAM (S TO P) MEMORY LIMIT ADDRESS REGISTER – OFFSET 58h ....................89
UPSTREAM (S TO P) MEMORY BASE ADDRESS UPPER 32-BIT REGISTER – OFFSET
...................................................................................................................................................89
UPSTREAM (S TO P) MEMORY LIMIT ADDRESS UPPER 32-BIT REGISTER – OFFSET
...................................................................................................................................................89
P_SERR# EVENT DISABLE REGISTER – OFFSET 64h.........................................................89
GPIO DATA AND CONTROL REGISTER – OFFSET 64h ......................................................91
SECONDARY CLOCK CONTROL REGISTER – OFFSET 68h...............................................91
P_SERR# STATUS REGISTER – OFFSET 68h........................................................................93
PORT OPTION REGISTER – OFFSET 74h .............................................................................93
SECONDARY MASTER TIMEOUT COUNTER REGISTER – OFFSET 80h...........................95
PRIMARY MASTER TIMEOUT COUNTER REGISTER – OFFSET 80h.................................95
CAPABILITY ID REGISTER – OFFSET B0h ...........................................................................95
NEXT POINTER REGISTER – OFFSET B0h...........................................................................95
SLOT NUMBER REGISTER – OFFSET B0h ...........................................................................95
CHASSIS NUMBER REGISTER – OFFSET B0h .....................................................................96
CAPABILITY ID REGISTER – OFFSET DCh..........................................................................96
NEXT ITEM POINTER REGISTER – OFFSET DCh ...............................................................96
POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET DCh .................................96
POWER MANAGEMENT DATA REGISTER – OFFSET E0h..................................................96
PPB SUPPORT EXTENSIONS REGISTER – OFFSET E0h ....................................................97
DATA REGISTER – OFFSET E0h............................................................................................97
CAPABILITY ID REGISTER – OFFSET E4h ...........................................................................97
NEXT POINTER REGISTER – OFFSET E4h...........................................................................97
HOT SWAP CONTROL AND STATUS REGISTER – OFFSET E4h ........................................97
CAPABILITY ID REGISTER – OFFSET E8h ...........................................................................98
NEXT POINTER REGISTER – OFFSET E8h...........................................................................98
VPD REGISTER – OFFSET E8h ..............................................................................................98
VPD DATA REGISTER – OFFSET ECh ..................................................................................98
MASTER ABORT ......................................................................................................................99
PARITY AND ERROR REPORTING ........................................................................................99
REPORTING PARITY ERRORS .............................................................................................100
SECONDARY IDSEL MAPPING............................................................................................100
Page 8 of 111
MARCH 2006 REVISION 1.12
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
PI7C8154B