pi7c8154b Pericom Semiconductor Corporation, pi7c8154b Datasheet - Page 50

• Manufacturer Part Number: pi7c8154b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0008
4.2
Delayed write completion transactions, comprised of I/O write and configuration write
transactions.
Delayed write completion transactions complete on the target bus, and the target response is queued
in the buffers. A delayed write completion transaction proceeds in the direction opposite that of the
original delayed write request; that is, a delayed write completion transaction proceeds from the
target bus to the initiator bus.
Delayed read request transactions, comprised of all memory read, I/O read, and
configuration read transactions.
Delayed read requests are terminated by target retry on the initiator bus and are queued in the
delayed transaction queue.
Delayed read completion transactions, comprised of all memory read, I/O read, &
configuration read transactions.
Delayed read completion transactions complete on the target bus, and the read data is queued in the
read data buffers. A delayed read completion transaction proceeds in the direction opposite that of
the original delayed read request; that is, a delayed read completion transaction proceeds from the
target bus to the initiator bus.
PI7C8154B does not combine or merge write transactions:
GENERAL ORDERING GUIDELINES
Independent transactions on primary and secondary buses have a relationship only when those
transactions cross PI7C8154B.
The following general ordering guidelines govern transactions crossing PI7C8154B:
PI7C8154B does not combine separate write transactions into a single write transaction—this
optimization is best implemented in the originating master.
PI7C8154B does not merge bytes on separate masked write transactions to the same DWORD
address—this optimization is also best implemented in the originating master.
PI7C8154B does not collapse sequential write transactions to the same address into a single
write transaction - the PCI Local Bus Specification does not permit this combining of
transactions.
The ordering relationship of a transaction with respect to other transactions is determined when
the transaction completes, that is, when a transaction ends with a termination other than target
retry.
Requests terminated with target retry can be accepted and completed in any order with respect
to other transactions that have been terminated with target retry. If the order of completion of
delayed requests is important, the initiator should not start a second delayed transaction until
the first one has been completed. If more than one delayed transaction is initiated, the initiator
should repeat all delayed transaction requests, using some fairness algorithm. Repeating a
delayed transaction cannot be contingent on completion of another delayed transaction.
Otherwise, a deadlock can occur.
Write transactions flowing in one direction have no ordering requirements with respect to write
transactions flowing in the other direction. PI7C8154B can accept posted write transactions on
both interfaces at the same time, as well as initiate posted write transactions on both interfaces
at the same time.
Page 50 of 111
MARCH 2006 REVISION 1.12
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
PI7C8154B