pi7c8154b Pericom Semiconductor Corporation, pi7c8154b Datasheet - Page 25

• Manufacturer Part Number: pi7c8154b
• Description: Asynchronous 2-port Pci Bridge
• Manufacturer: Pericom Semiconductor Corporation

06-0008
2.6
2.6.1
Depending on the command type, PI7C8154B can support multiple data phase PCI transactions.
For detailed descriptions of how PI7C8154B imposes disconnect boundaries, see Section 2.6.4 for
write address boundaries and Section 2.7.3 read address boundaries.
WRITE TRANSACTIONS
Write transactions are treated as either posted write or delayed write transactions. Table 2-2 shows
the method of forwarding used for each type of write operation.
Table 2-2 WRITE TRANSACTION FORWARDING
MEMORY WRITE TRANSACTIONS
Posted write forwarding is used for “Memory Write” and “Memory Write and Invalidate”
transactions.
When PI7C8154B determines that a memory write transaction is to be forwarded across the bridge,
PI7C8154B asserts DEVSEL# with medium decode timing and TRDY# in the next cycle, provided
that enough buffer space is available in the posted memory write queue for the address and at least
one DWORD of data. Under this condition, PI7C8154B accepts write data without obtaining
access to the target bus. The PI7C8154B can accept one DWORD of write data every PCI clock
cycle. That is, no target wait state is inserted. The write data is stored in an internal posted write
buffers and is subsequently delivered to the target. The PI7C8154B continues to accept write data
until one of the following events occurs:
When one of the last two events occurs, the PI7C8154B returns a target disconnect to the
requesting initiator on this data phase to terminate the transaction.
Once the posted write data moves to the head of the posted data queue, PI7C8154B asserts its
request on the target bus. This can occur while PI7C8154B is still receiving data on the initiator
bus. When the grant for the target bus is received and the target bus is detected in the idle
condition, PI7C8154B asserts FRAME# and drives the stored write address out on the target bus.
On the following cycle, PI7C8154B drives the first DWORD of write data and continues to transfer
write data until all write data corresponding to that transaction is delivered, or until a target
termination is received. As long as write data exists in the queue, PI7C8154B can drive one
DWORD of write data in each PCI clock cycle; that is, no master wait states are inserted. If write
data is flowing through PI7C8154B and the initiator stalls, PI7C8154B will signal the last data
phase for the current transaction at the target bus if the queue empties. PI7C8154B will restart the
follow-on transactions if the queue has new data.
The initiator terminates the transaction by de-asserting FRAME# and IRDY#.
An internal write address boundary is reached, such as a cache line boundary or an aligned
4KB boundary, depending on the transaction type.
The posted write data buffer fills up.
Type of Transaction
Memory Write
Memory Write and Invalidate
Memory Write to VGA memory
I/O Write
Type 1 Configuration Write
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Type of Forwarding
Posted (except VGA memory)
Posted
Delayed
Delayed
Delayed
MARCH 2006 REVISION 1.12
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
PI7C8154B