pnx1500 NXP Semiconductors, pnx1500 Datasheet - Page 114

• Manufacturer Part Number: pnx1500
• Description: Pnx15xx Series Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
PNX15XX_SER_3
Product data sheet
2.4 The Programmable DCS Apertures
the program is in a phase where it is planned to be used). This creates random
addresses that can target the APERT1 aperture. Therefore the load may generate a
transaction on the PCI bus that may have some side effects. Furthermore the
performance are deteriorated by a long CPU stall cycle that is dependent on the
completion of PCI bus transaction (the CPU does not continue unless the read has
completed). To avoid these long CPU stall cycles it is recommended to disable the
APERT1 when not used. This is achieved by setting the right mode into the TM3260
D C _ L O C K _ C T L M M I O r e g i s t e r o r b y s e t t i n g T M 3 2 _ A P E R T 1 _ L O a n d
TM32_APERT1_HI to the same value.
The address range defined by the content of DCS_DRAM_LO or DCS_DRAM_HI
must not overlap the address ranges of the other apertures on the DCS bus. This can
happen temporarily when changing either the DCS_DRAM_LO or the
DCS_DRAM_HI. Therefore any change of the DCS_DRAM_LO or DCS_DRAM_HI
registers must be done by first disabling the DCS DRAM aperture. This is achieved by
starting to change DCS_DRAM_LO or DCS_DRAM_HI such that DCS_DRAM_LO is
greater than DCS_DRAM_HI.
Similar constraints apply respectively to PCI_BASE1_LO and PCI_BASE1_HI, and
PCI_BASE2_LO and PCI_BASE2_HI.
•
Requests from the PCI bus or the TM3260 targeting the DRAM aperture do not
go through the DCS bus. Instead the requests are routed directly to the MMI
module. The DRAM aperture defined in the DCS bus is exclusively defined for the
boot module. When the boot module is programmed to boot PNX15xx Series
from an EEPROM, the boot module fetches write commands from the EEPROM.
Each write command is sent to the DCS bus. If the write address falls between
the aperture defined by DCS_DRAM_LO and DCS_DRAM_HI,
then the write data is transferred to the MMI module. This gate allows transfer to
the main memory, a binary program, (that is stored into the EEPROM) for the
TM3260. The bus connecting the module to the MMI is referenced as the MTL
bus (see
Section 10. on page 3-30 Figure
Rev. 3 — 17 March 2006
Chapter 3: System On Chip Resources
3).
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
Section
2.4.1,
3-5