pnx1500 NXP Semiconductors, pnx1500 Datasheet - Page 674

• Manufacturer Part Number: pnx1500
• Description: Pnx15xx Series Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
3. Register Descriptions
PNX15XX_SER_3
Product data sheet
3.1 Register Summary
The two transmit queues can also be configured to support a generic
Quality-of-Service (QoS) system: a high-priority queue provides high quality of
service for packets; a low priority queue runs when possible.
A receive time-stamp indicates the exact moment in time a packet has been received.
Receive blocking filters are used to identify received packets that are not addressed
to this Ethernet station, so that they can be discarded. The Rx filters include a perfect
address filter, a hash filter, and four pattern-matching filters.
Wake-on-LAN power management support makes it possible to wake the system up
from a power-down state (a state in which some of the clocks are switched off) when
wake-up frames are received over the LAN. Wake-up frames are recognized by the
receive filtering modules or by a Magic Frame detection technology. System wake-up
occurs by triggering an interrupt.
An interrupt logic block raises and masks interrupts and keeps track of the cause of
interrupts. The interrupt block sends interrupt request signals to the CPU. Interrupts
can be enabled, cleared, and set by software.
Support for IEEE 802.3/clause 31 flow control is implemented in the Flow Control
block. Receive flow-control frames are automatically handled by the LAN100.
Transmit flow-control frames can be initiated by software. In half-duplex mode, the
flow-control module will generate back pressure by sending out continuous preamble
only interrupted by pauses to prevent the jabber limit.
The LAN100 has both a standard IEEE 802.3/clause 22 Media Independent Interface
(MII) bus and a Reduced Media Independent Interface (RMII) to connect to an
external Ethernet PHY chip [3]. MII or RMII mode can be selected by a bit in the
LAN100 Command register. The standard nibble-wide MII interface allows a
low-speed data connection to the PHY chip at speeds of 2.5 MHz at 10 Mbit/s or 25
MHz at 100 Mbit/s. The RMII interface allows connection to the PHY with low
pin-count and double-speed data clock. Registers in the PHY chip are accessed via
the MMIO interface through the serial management connection of the MII bus
operating at 2.5 MHz.
The base address for LAN100 MMIO registers begins at offset 0x07,2000 with
respect to MMIO_BASE.
After a hard or soft reset via the RegReset bit of the Command register, all bits in all
registers are reset to 0, unless shown otherwise in
Reading write-only registers will return a read error. Writing read-only registers will
return a write error. Unused or resrved bits must be ignored on reads and written as
0.
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A non-real-time queue sends packets immediately.
Rev. 3 — 17 March 2006
Chapter 23: LAN100 — Ethernet Media Access Controller
Table
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
2.
PNX15xx Series
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