pnx1500 NXP Semiconductors, pnx1500 Datasheet - Page 671

• Manufacturer Part Number: pnx1500
• Description: Pnx15xx Series Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
2. Functional Description
PNX15XX_SER_3
Product data sheet
2.1 Chip I/O and System Interconnections
Figure 1
On the left-hand side, the LAN100 is connected to the off-chip Ethernet PHY using
the Media Independent Interface (MII) or Reduced Media Independent Interface
(RMII), which includes transmit, receive, and management connections. On the
right-hand side, the LAN100 is connected to the on-chip system buses:
Figure 1:
•
•
(R)MII Tx
(R)MII Rx
The MMIO control port of the LAN100 allows CPU access to the LAN100’s
internal registers via the internal DCS bus of the PNX15xx Series. The LAN100
MMIO port is a slave on the DCS bus.
The Direct Memory Access (DMA) port of the LAN100 performs DMA via the
internal MTL bus of the PNX15xx Series. The LAN100 can initiate transactions
while it is a master on the MTL bus. The LAN100 has multiple DMA interfaces to
allow both non-real-time and real-time transmit modes, and receive mode.
PHY
MIIM
presents a simplified view of the I/O interfaces and system interconnection.
Simplified LAN100 I/O Block Diagram
LAN100
Rev. 3 — 17 March 2006
Chapter 23: LAN100 — Ethernet Media Access Controller
Non-real-time transmit
Real-time transmit
Descriptors
Descriptors
Descriptors
Descriptors
Descriptors
Descriptors
Receive
Status
Status
Status
Status
Status
Status
Data
Data
Data
Data
Data
Data
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
Control
Master
MMIO
Slave
DMA
MTL
Bus
DCS
Bus
Memory
CPU
23-2