pnx1500 NXP Semiconductors, pnx1500 Datasheet - Page 517

• Manufacturer Part Number: pnx1500
• Description: Pnx15xx Series Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
PNX15XX_SER_3
Product data sheet
Figure 5:
SCK
WS
SDx
left channel datan (16)
Example Codec Frame Layout for a Crystal Semiconductor CS4218
0
1
2
3
2.8 Data Bus Latency and HBE
It is legal to program the control field positions within the frame such that CC1 and
CC2 overlap each other and/or left and right data fields. If two fields are defined to
start at the same bit position, the priority is left (highest), right, CC1 then CC2. The
field with the highest priority will be emitted starting at the conflicting bit position. If a
field f2 is defined to start at a bit position i that falls within a field f1 starting at a lower
bit position, f2 will be emitted starting from i and the rest of f1 will be lost. Any bit
positions not belonging to a data or control field will be emitted as zero.
If a field is defined to start at a bit position such that the end of the field goes beyond
the end of the frame, the data beyond the end of the frame (as defined by the active
edge of WS) is lost.
Figure 5
by setting POLARITY=1, LEFTPOS=0, RIGHTPOS=32, DATAMODE=0, SSPOS=0,
CLOCK_EDGE=1, WS_PULSE=1, CC1_POS= 16, CC1_EN=1, CC2_POS=48 and
CC2_EN=1.
Note that frames are generated (externally or internally) even when
TRANS_ENABLE is de-asserted. Writes to CC1 and CC2 should only be done after
TRANS_ENABLE is asserted. The ‘first’ CC values will then go out on the next frame.
The Audio Out unit relies on the FIFO buffers within the DMA interface adapter as
well as an output holding register that holds a single mono sample or single stereo
sample pair. For Audio Out there are four separate stereo output channels and each
output channel has one output holding register. The holding register width is 64 bits.
Under normal operation, the DMA interface adapter provides samples from memory
fast enough to avoid any missing samples. Meanwhile, data is being emitted from one
64-byte hardware buffer and holding register. If the data bus arbiter is set up with an
insufficient latency guarantee, the situation can arise that the hardware FIFO buffer
within the DMA interface adapter is not refilled in time and the buffer and holding
register are exhausted by the time a new output sample is due. In that case the HBE
flag is raised to indicate a bandwidth error. The last sample for each channel will be
repeated until the buffer is refreshed. The HBE condition is sticky and can only be
cleared by an explicit ACK_HBE. This condition indicates an incorrect setting of the
data bus bandwidth arbiter.
Table 6
modes. The right most column in the table indicates the maximum tolerable latency
for Audio Out under normal operating condition. To sustain error free audio playback,
one 64-byte DMA transfer must be completed within the maximum latency period
LSB
15 16
shows the maximum tolerable latency for a number of common operating
CC1(16)
shows a 64-bit frame suitable for use with the CS4218 codec. It is obtained
Rev. 3 — 17 March 2006
LSB
31 32
right channel data
n
(16)
LSB
47 48
CC2(16)
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
Chapter 15: Audio Output
62 63
LSB
left data
0
1
n
+1(16)
15-10