pnx1500 NXP Semiconductors, pnx1500 Datasheet - Page 653

• Manufacturer Part Number: pnx1500
• Description: Pnx15xx Series Connected Media Processor
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Volume 1 of 1
Table 2: VLD STATUS
PNX15XX_SER_3
Product data sheet
Name
VLD Command Done
Start Code Detected
Bitstream Error
DMA Input Done
DMA Macroblock
Header Output Done
DMA Run/Level
Output Done
RL overflow Error
3.2.2 VLD Interrupt Enable (VLD_IE)
3.2.3 VLD Control (VLD_CTL)
Size
(Bits) Description
1
1
1
1
1
1
1
When an error occurs in the VLD, the corresponding error flag (Bitstream error or RL
overflow error) is set and an interrupt is generated if corresponding bits in the VLD_IE
register is set. Refer to section
mechanism.
This VLD_IE read/write register allows the CPU to control the initiation of the interrupt
for the corresponding bits in the VLD_MC_STATUS register. Writing a one to any of
these bits in the VLD_IE register enables the interrupt for the corresponding bit in the
status register.
When VLD detects a new slice start code in the bit-stream, it writes the lower 8-bits of
the start code into the slice_start_code field of the VLD_CTL register before
interrupting the CPU. When re-started, the VLD reads the slice_start_code from the
VLD_CTL register and writes this value into bits 16-23 of the last word in the first
mb_header and sets the mb_first bit to 1. To allow the CPU to switch bitstream at the
slice level, CPU can write the desired slice start code and slice_start_code_strobe in
the VLD control register. The value of ‘1’ in the slice_start_code_strobe will cause the
VLD to update the slice_start_code field with the given slice_start_code value. The
other fields in the VLD_CTL register are not updated when the input data contains a
value of ‘1’ in the slice_start_code_strobe field. The slice_start_code_strobe bit is
always read as 0. The CPU must write the slice_start_code only when the VLD is not
active. In order to update the DMA_INPUT_DONE_MODE fields, the
slice_start_code_strobe bit value must be set to ‘0’.
The use of the DMA_INPUT_DONE_MODE bit is described in
Logic ‘1’ indicates successful completion of current command. This bit is cleared by issuing
a new command.
Logic ‘1’ indicates VLD encountered 0x000001 while executing current command.
This bit is cleared by writing a logic ‘1’ to it.
Logic ‘1’ indicates VLD encountered an illegal Huffman code or an unexpected start code.
Refer to
cleared by writing a logic ‘1’ to it.
Conditions for setting this bit depends on the value of the DMA_Input_Done field in the
VLD_CTL register. Refer to
details. This bit is cleared by writing a logic ‘1’ to it.
Logic ‘1’ indicates that the macroblock header DMA write transfer has completed.
Logic ‘1’ indicates that the Run/Level DMA write transfer has completed.
Logic ‘1’ indicates Overflow of run/level values within a block.
Refer to
This bit is cleared by writing a logic ‘1’ to it.
Section 3.4 Error Handling
Section 3.4
Rev. 3 — 17 March 2006
for details on the error handling procedure.
Chapter 21: MPEG-1 and MPEG-2 Variable Length Decoder
Section 3 VLD Control
Section 3.4
for details on the error handling procedure. This bit is
for details on the error handling
and
Section 3.3 VLD Operation
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
Table
3.
for
21-5